AT25SL641-DWF datasheet(2/76 Pages) DIALOG

2 / 76 page

DS-25SL641–113F–12/2018

Features

Single 1.7V - 2.0V Supply

Serial Peripheral Interface (SPI) and Quad Peripheral Interface (QPI) Compatible

Supports SPI Modes 0 and 3

Supports Dual Output Read and Quad I/O Program and Read

Supports QPI Program and Read

133 MHz Maximum Operating Frequency

Clock-to-Output (t

V1) of 6 ns

Up to 66 MB/s Continuous Data Transfer Rate

Full Chip Erase

Flexible, Optimized Erase Architecture for Code and Data Storage Applications

0.6 ms Typical Page Program (256 Bytes) Time

60 ms Typical 4-Kbyte Block Erase Time

200 ms Typical 32-Kbyte Block Erase Time

350 ms Typical 64-Kbyte Block Erase Time

Hardware Controlled Locking of Status Registers via WP Pin

4 Kbit secured One-Time Programmable Security Register

Hardware Write Protection

Serial Flash Discoverable Parameters (SFDP) Register

Flexible Programming

Byte/Page Program (1 to 256 Bytes)

Dual or Quad Input Byte/Page Program (1 to 256 Bytes)

Erase/Program Suspend and Resume

JEDEC Standard Manufacturer and Device ID Read Methodology

Low Power Dissipation

2 µA Deep Power-Down Current (Typical)

10 µA Standby current (Typical)

5 mA Active Read Current (Typical)

Endurance: 100,000 program/erase cycles (4KB, 32KB or 64KB blocks)

Data Retention: 20 Years

Industrial Temperature Range: -40°C to +85°C

Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options

8-lead SOIC (208-mil)

8-pad DFN (6 x 5 x 0.6 mm)

8-ball WLCSP (dBGA)

Die in Wafer Form

AT25SL641

64-Mbit, 1.7V Minimum

SPI Serial Flash Memory with Dual I/O, Quad I/O and QPI Support

AT25SL641-DWF 데이터시트(PDF) 2 Page - Dialog Semiconductor