PCF8553DTTSLASHAJ datasheet(38/51 Pages) NXP

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NXP Semiconductors

PCF8553

40 × 4 LCD segment driver

15 Application information

15.1 Power-on reset

The built-in POR block acts on the rising edge of the VDD supply voltage. Depending

on the VDD rising edge in the application, the POR may not work properly. Therefore to

ensure proper device operation it is required to send nine clock pulses immediately after

power-on (see also UM10204).

15.2 I2C acknowledge after power-on

If the bus does not show an acknowledge at the first access, the command should be

sent a second time.

15.3 Resistors on I/O pins

The pins A0, A1, PORE, and IFS comprise internal, latching pull-down devices, which

keep these inputs at a low potential when left open. If an input is supposed to be at logic

0 potential, this pin can be either connected to VSS or left open.

In case a pin is supposed to be at logic 1 potential, it must be connected to VDD to avoid

any cross-current during power-up. A series resistance between VDD and the associated

pin must not exceed 1 kΩ to ensure proper functionality.

PCF8553

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 20 April 2021

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PCF8553DTT/AJ 데이터시트(PDF) 38 Page - NXP Semiconductors