AD9517-2ASLASHPCBZ datasheet(48/80 Pages) AD

48 / 80 page

AD9517-2

Data Sheet

Rev. F | Page 48 of 80

910

INPUT TO VCO DIVIDER

INPUT TO CHANNEL DIVIDER

OUTPUT OF

CHANNEL DIVIDER

SYNC PIN

14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT

CHANNEL DIVIDER OUTPUT STATIC

CHANNEL DIVIDER

OUTPUT CLOCKING

CHANNEL DIVIDER

OUTPUT CLOCKING

Figure 57. SYNC Timing When VCO Divider Is Used—CLK or VCO Is Input

INPUT TO CLK

IINPUT TO CHANNEL DIVIDER

OUTPUT OF

CHANNEL DIVIDER

SYNC PIN

14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT

910

CHANNEL DIVIDER OUTPUT STATIC

CHANNEL DIVIDER

OUTPUT CLOCKING

CHANNEL DIVIDER

OUTPUT CLOCKING

Figure 58. SYNC Timing When VCO Divider Is Not Used—CLK Input Only

A sync operation brings all outputs that have not been excluded

(by the nosync bit) to a preset condition before allowing the

outputs to begin clocking in synchronicity. The preset

condition takes into account the settings in each of the

channel’s start high bit and its phase offset. These settings

govern both the static state of each output when the sync

operation is happening and the state and relative phase of the

outputs when they begin clocking again upon completion of the

sync operation. Between outputs and after synchronization, this

allows for the setting of phase offsets.

The AD9517 outputs are in pairs, sharing a channel divider per

pair (two pairs of pairs, four outputs, in the case of CMOS).

The synchronization conditions apply to both outputs of a pair.

Each channel (a divider and its outputs) can be excluded from

any sync operation by setting the nosync bit of the channel.

Channels that are set to ignore SYNC (excluded channels) do

not set their outputs static during a sync operation, and their

outputs are not synchronized with those of the nonexcluded

channels.

Clock Outputs

The AD9517 offers three different output level choices:

LVPECL, LVDS, and CMOS. OUT0 to OUT3 are LVPECL

differential outputs; and OUT4 to OUT7 are LVDS/CMOS

outputs. These outputs can be configured as either LVDS

differential or as pairs of single-ended CMOS outputs.

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