ICS601-02

Low Phase Noise Clock Multiplier

MDS 601-02 D

3

Revision 111204

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA•95126 • (408) 295-9800tel • www.icst.com

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10.0E+0

100.0E+0

1.0E+3

10.0E+3

100.0E+3

1.0E+6

10.0E+6

Offset from Carrier (Hz)

Figure 1. Phase Noise of ICS601-02 at 125 MHz out, 25 MHz crystal input, VDD =

3.3 V.

Figure 1 shows a typical phase noise measurement in a 125 MHz system. There are a few simple steps that can be

taken to achieve these levels of phase noise from the ICS601-02. Variations in VDD will increase the phase noise, so

it is important to have a stable, low noise supply voltage at the device. Use decoupling capacitors of 0.1 µF in parallel

with 0.01 µF. It is important to have these capacitors as close as possible to the ICS601-02 supply pins.

Disabling the REFOUT clock is also important for achieving low phase noise; lab tests have shown that this can

reduce the phase noise by as much as 10 dBc/Hz.

Achieving Low Phase Noise

External Components/Crystal Selection

The ICS601-02 requires a minimum number of external components for proper operation. Decoupling capacitors of

0.01 µF and 0.1 µF should be connected between VDD and GND, as close to the part as possible. A series

termination resistor of 33

Ω may be used for the clock output. The crystal must be connected as close to the chip as

possible. The crystal should be fundamental mode, parallel resonant. Do not use third overtone. For exact tuning

when using a crystal, capacitors should be connected from pins X1 to ground and X2 to ground. In general, the value

of these capacitors is given by the following equation, where CL is the crystal load capacitance: Crystal caps (pF) =

(CL-5) x 2. So for a crystal with 16 pF load capacitance, two 22 pF caps can be used. For any given board layout, ICS

can measure the board capacitance and recommend the exact capacitance value to use.