ICS601-02

Low Phase Noise Clock Multiplier

MDS 601-02 D

1

Revision 111204

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA•95126 • (408) 295-9800tel • www.icst.com

The ICS601-02 is a low cost, low phase noise, high

performance clock synthesizer for any application that

requires low phase noise and low jitter. The ICS601 is

ICS’ lowest phase noise multiplier. Using ICS’ patented

analog and digital Phase Locked Loop (PLL)

techniques, the chip accepts a 10-27 MHz crystal or

clock input, and produces output clocks up to 170

MHz at 3.3 V. A separate supply pin is provided so that

the output can be 2.5 V.

This product is intended for clock generation. It has low

output jitter (variation in the output period), but input to

output skew and jitter are not defined nor guaranteed.

For applications which require defined input to output

timing, use the ICS670-01.

Block Diagram

Description

Features

• Packaged in 16 pin SOIC (Pb free)

• Uses fundamental 10 - 27 MHz crystal, or clock

• Patented PLL with the lowest phase noise

• Output clocks up to 170 MHz at 3.3 V

• Low phase noise: -132 dBc/Hz at 10 kHz

• Output Enable function tri states outputs

• Low jitter - 18 ps one sigma

• Full swing CMOS outputs with 25 mA drive

capability at TTL levels

• Advanced, low power, sub-micron CMOS process

• Industrial temperature

• 3.3 V or 5 V core VDD. Output clock can operate

down to 2.5 V

Reference

Divide

Phase

Comparator

Crystal

Oscillator

ROM Based

Multipliers

VCO

Divide

Charge

Pump

Loop

Filter

VCO

Output

Buffer

X1/ICLK

X2

S0

S1

VDD

GND

OE

CLK

S3 S2

VDDP

Optional crystal

capacitors

needed

for accurate

tuning

(not shown)