LAN9255

DS00003646B-page 6

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2020-2021 Microchip Technology Inc.

3.0

LAN9255 DEVICE SPECIFICATIONS

This section details device specifications that are unique to the LAN9255 and/or supersede those included in the

LAN9253 and SAM E53J data sheets.

3.1

Optimal Interfacing between LAN9253 and SAM E53J

The following guidelines will provide optimal interfacing between the internal LAN9253 and SAM E53J die.

• The following connections are required between die for SPI/QSPI operation:

• ESC EEPROM connected to the LAN9253 is optional

• Refer to the LAN9253 Data Sheet for information on configuration straps required to enable EEPROM emulation

• The 25MHz clock from the LAN9253 may be optionally used to feed the SAM E53J

3.2

Optimal EtherCAT Interfacing

• The EtherCAT RUN and EtherCAT ERROR LEDs can be used. Refer to the LAN9253 Data Sheet for additional

information.

3.2.1

IMPLEMENTING ETHERNET

TABLE 3-1:

SPI/QSPI CONNECTIONS

SPI Function

LAN9253 Pins

SAM E53J Pins

SCK

41

40

SCS#

101

42

SIO0

38

33

SIO1

26

34

SIO2

24

35

SIO3

71

36

TABLE 3-2:

RMII INTERFACE

RMII Function

Pin Name

LAN9255 Pin Number

TXEN

PA17

68

TXD0

PA18

69

TXD1

PA19

73

RXDV

PA16

67

RXD0

PA13

62

RXD1

PA12

61

RXER

PA15

64

MDIO

PA21

87

MDC

PA20

84