PCIMX6DP5AVT2AB datasheet(83/168 Pages) NXP

83 / 168 page

Electrical Characteristics

i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018

NXP Semiconductors

4.12.4.4

Bus Operation Condition for 3.3 V and 1.8 V Signaling

Signaling level of SD/eMMC4.3 and eMMC4.4/4.41 modes is 3.3 V. Signaling level of SDR104/SDR50

mode is 1.8 V. The DC parameters for the NVCC_SD1, NVCC_SD2, and NVCC_SD3 supplies are

identical to those shown in Table 22, “GPIO I/O DC Parameters,” on page 40.

4.12.5

Ethernet Controller (ENET) AC Electrical Specifications

4.12.5.1

ENET MII Mode Timing

This subsection describes MII receive, transmit, asynchronous inputs, and serial management signal

timings.

4.12.5.1.1

MII Receive Signal Timing (ENET_RX_DATA3,2,1,0, ENET_RX_EN,

ENET_RX_ER, and ENET_RX_CLK)

The receiver functions correctly up to an ENET_RX_CLK maximum frequency of 25 MHz + 1%. There

is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the

ENET_RX_CLK frequency.

Figure 42 shows MII receive signal timings. Table 53 describes the timing parameters (M1–M4) shown in

the figure.

Figure 42. MII Receive Signal Timing Diagram

1 ENET_RX_EN, ENET_RX_CLK, and ENET0_RXD0 have the same timing in 10 Mbps 7-wire interface mode.

Table 53. MII Receive Signal Timing

Characteristic1

Min

Max

Unit

ENET_RX_DATA3,2,1,0, ENET_RX_EN, ENET_RX_ER to

ENET_RX_CLK setup

5—

ENET_RX_CLK to ENET_RX_DATA3,2,1,0, ENET_RX_EN,

ENET_RX_ER hold

5—

ENET_RX_CLK pulse width high

35%

65%

ENET_RX_CLK period

ENET_RX_CLK pulse width low

35%

65%

ENET_RX_CLK period

ENET_RX_CLK (input)

ENET_RX_DATA3,2,1,0

ENET_RX_ER

ENET_RX_EN

(inputs)

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