PCIMX6DP5AVT2AB datasheet(84/168 Pages) NXP

84 / 168 page

i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018

NXP Semiconductors

Electrical Characteristics

4.12.5.1.2

MII Transmit Signal Timing

(ENET_TX_DATA3,2,1,0, ENET_TX_EN, ENET_TX_ER, and ENET_TX_CLK)

The transmitter functions correctly up to an ENET_TX_CLK maximum frequency of 25 MHz + 1%.

There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed

twice the ENET_TX_CLK frequency.

Figure 43 shows MII transmit signal timings. Table 54 describes the timing parameters (M5–M8) shown

in the figure.

Figure 43. MII Transmit Signal Timing Diagram

1 ENET_TX_EN, ENET_TX_CLK, and ENET0_TXD0 have the same timing in 10-Mbps 7-wire interface mode.

4.12.5.1.3

MII Asynchronous Inputs Signal Timing (ENET_CRS and ENET_COL)

Figure 44 shows MII asynchronous input timings. Table 55 describes the timing parameter (M9) shown in

the figure.

Figure 44. MII Async Inputs Timing Diagram

Table 54. MII Transmit Signal Timing

Characteristic1

Min

Max

Unit

ENET_TX_CLK to ENET_TX_DATA3,2,1,0, ENET_TX_EN,

ENET_TX_ER invalid

5—

ENET_TX_CLK to ENET_TX_DATA3,2,1,0, ENET_TX_EN,

ENET_TX_ER valid

—20

ENET_TX_CLK pulse width high

35%

65%

ENET_TX_CLK period

ENET_TX_CLK pulse width low

35%

65%

ENET_TX_CLK period

ENET_TX_CLK (input)

ENET_TX_DATA3,2,1,0

ENET_TX_ER

ENET_TX_EN

(outputs)

ENET_CRS, ENET_COL

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