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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PCIMX6DP5AVT2AB 데이터시트(PDF) 106 Page - NXP Semiconductors |
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PCIMX6DP5AVT2AB 데이터시트(HTML) 106 Page - NXP Semiconductors |
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106 / 168 page  i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018 106 NXP Semiconductors Electrical Characteristics Figure 65 depicts the synchronous display interface timing for access level. The DISP_CLK_DOWN and DISP_CLK_UP parameters are register-controlled. Table 66 lists the synchronous display interface timing characteristics. Figure 65. Synchronous Display Interface Timing Diagram—Access Level Table 66. Synchronous Display Interface Timing Characteristics (Access Level) ID Parameter Symbol Min Typ1 1The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be chip specific. Max Unit IP16 Display interface clock low time Tckl Tdicd-Tdicu-1.24 Tdicd2-Tdicu3 2 Display interface clock down time 3 Display interface clock up time where CEIL(X) rounds the elements of X to the nearest integers towards infinity. Tdicd-Tdicu+1.24 ns IP17 Display interface clock high time Tckh Tdicp-Tdicd+Tdicu-1.24 Tdicp-Tdicd+Tdicu Tdicp-Tdicd+Tdicu+1.2 ns IP18 Data setup time Tdsu Tdicd-1.24 Tdicu — ns IP19 Data holdup time Tdhd Tdicp-Tdicd-1.24 Tdicp-Tdicu — ns IP20o Control signals offset times (defined for each pin) Tocsu Tocsu-1.24 Tocsu Tocsu+1.24 ns IP20 Control signals setup time to display interface clock (defined for each pin) Tcsu Tdicd-1.24-Tocsu%Tdicp Tdicu — ns IP19 IP18 IP20 VSYNC IP17 IP16 DRDY HSYNC other controls IP20o local start point Tdicd Tdicu IPP_DISP_CLK IPP_DATA Tdicd 1 2 ---Tdiclk ceil × 2 DISP_CLK_DOWN × DI_CLK_PERIOD ----------------------------------------------------------- = Tdicu 1 2 ---Tdiclk ceil × 2 DISP_CLK_UP × DI_CLK_PERIOD ------------------------------------------------ = |
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