IMX7ULPIECB2 datasheet(21/112 Pages) NXP

21 / 112 page

Table 1. i.MX 7ULP modules list (continued)

Block Name

Block Mnemonic

Subsystem

Power

Domain

Brief description

up of the Cortex-A processor when it is

in low power mode.

Watchdog Timer

WDOG0-2

Timers

AD, RT

The Watchdog Timer (WDOG) module

keeps a watch on the system

functioning and resets it in case of its

failure. Reasons for failure include run-

away software code and the stoppage

of the system clock that in a safety

critical system can lead to serious

consequences. In such cases, the

WDOG brings the system into a safe

state of operation. The WDOG monitors

the operation of the system by

expecting periodic communication from

the software, generally known as

servicing or refreshing the WDOG. If

this periodic refreshing does not occur,

the WDOG resets the system. WDOG0

is in the real-time domain. WDOG1 and

WDOG2 are in the application domain.

XRDC Manager

MGR

Multicore Peripherals

and Resource Domain

Control submodules

The XRDC Manager (MGR) submodule

coordinates all programming model

reads and writes.

XRDC Master

Domain Assignment

Controller

MDAC

Multicore Peripherals

and Resource Domain

Control submodules

AD, RT

The XRDC Master Domain Assignment

Controller (MDAC) submodule handles

resource assignments and generation of

the domain identifiers.

XRDC Memory

Region Controller

MRC

Multicore Peripherals

and Resource Domain

Control submodules

AD, RT

The XRDC Memory Region Controller

(MRC) submodule implements the

access controls for slave memories

based on the pre-programmed region

descriptor registers.

XRDC Peripheral

Access Controller

PAC

Multicore Peripherals

and Resource Domain

Control submodules

AD, RT

The XRDC Peripheral Access Controller

(PAC) implements the access controls

for slave peripherals based on the pre-

programmed domain access control

registers.

2 Clocking

Clocking

i.MX 7ULP Applications Processor—Industrial, Rev. 1, 07/2021

NXP Semiconductors

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