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DLPA2000 데이터시트(PDF) 54 Page - Texas Instruments |
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DLPA2000 데이터시트(HTML) 54 Page - Texas Instruments |
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54 / 63 page ![]() Table 10-5. High Speed PCB Signal Routing Matching Requirements SIGNAL GROUP LENGTH MATCHING(1) (2) (3) INTERFACE SIGNAL GROUP REFERENCE SIGNAL MAX MISMATCH(4) UNIT DMD(5) DMD_HS_WDATA_C_P DMD_HS_WDATA_C_N DMD_HS_CLK_P DMD_HS_CLK_N ±1.0 (±25.4) in (mm) DMD_HS_WDATA_D_P DMD_HS_WDATA_D_N DMD_HS_WDATA_E_P DMD_HS_WDATA_E_N DMD_HS_WDATA_F_P DMD_HS_WDATA_F_N DMD DMD_HS_WDATA_x_P DMD_HS_WDATA_x_N ±0.025 (±0.635) in (mm) DMD DMD_HS_CLK_P DMD_HS_CLK_N ±0.025 (±0.635) in (mm) DMD DMD_LS_WDATA DMD_LS_RDATA DMD_LS_CLK ±0.2 (±5.08) in (mm) DMD DMD_DEN_ARSTZ N/A N/A in (mm) (1) The length matching values apply to PCB routing lengths only. Internal package routing mismatch associated with the DLPC34xx controller or the DMD require no additional consideration. (2) Training is applied to DMD HS data lines. This is why the defined matching requirements are slightly relaxed compared to the LS data lines. (3) DMD LS signals are single ended. (4) Mismatch variance for a signal group is always with respect to the reference signal. (5) DMD HS data lines are differential, thus these specifications are pair-to-pair. DLPC3420 DLPS232 – OCTOBER 2021 www.ti.com 54 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DLPC3420 |
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