MPC8347ECVRADDB datasheet(94/99 Pages) NXP

94 / 99 page

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

Ordering Information

However, while HRESET is asserted, these pins are treated as inputs, and the value on these pins is latched

when PORESET deasserts. Then the input receiver is disabled and the I/O circuit takes on its normal

function. Careful board layout with stubless connections to these pull-up/pull-down resistors coupled with

the large value of the pull-up/pull-down resistor should minimize the disruption of signal quality or speed

for the output pins.

21.7

Pull-Up Resistor Requirements

The MPC8347EA requires high resistance pull-up resistors (10 k

Ω is recommended) on open-drain pins,

including I2C pins, and IPIC interrupt pins.

For more information on required pull-up resistors and the connections required for the JTAG interface,

refer to application note AN2931, “PowerQUICC Design Checklist.”

22 Ordering Information

This section presents ordering information for the device discussed in this document, and it shows an

example of how the parts are marked.

NOTE

The information in this document is accurate for revision 3.x silicon and

later (in other words, for orderable part numbers ending in A or B). For

information on revision 1.1 silicon and earlier versions, see the MPC8347E

PowerQUICC II Pro Integrated Host Processor Hardware Specifications

(Document Order No. MPC8347EEC).

22.1

Part Numbers Fully Addressed by This Document

Table 70 shows an analysis of the Freescale part numbering nomenclature for the MPC8347EA. The

individual part numbers correspond to a maximum processor core frequency. Each part number also

contains a revision code that refers to the die mask revision number. For available frequency configuration

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