MPC8560CPX667JC datasheet(27/108 Pages) NXP

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MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2

Freescale Semiconductor

Ethernet: Three-Speed, MII Management

7.2.2 MII AC Timing Specifications

This section describes the MII transmit and receive AC timing specifications.

7.2.2.1

MII Transmit AC Timing Specifications

Table 23 provides the MII transmit AC timing specifications.

Figure 10 shows the MII transmit AC timing diagram.

Figure 10. MII Transmit AC Timing Diagram

Table 23. MII Transmit AC Timing Specifications

At recommended operating conditions with LVDD of 3.3 V ± 5%, or LVDD=2.5V ± 5%.

Parameter/Condition

Symbol 1

Min

Typ

Max

Unit

TX_CLK clock period 10 Mbps

tMTX

—400

—

TX_CLK clock period 100 Mbps

tMTX

—40

—

TX_CLK duty cycle

tMTXH/tMTX

—

TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay

tMTKHDX

TX_CLK data clock rise and fall time

tMTXR, tMTXF

2,3

1.0

—

4.0

Note:

1.The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX

symbolizes MII transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are

invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters

representing the clock of a particular functional. For example, the subscript of tMTX represents the MII(M) transmit

(TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2.Signal timings are measured at 0.7 V and 1.9 V voltage levels.

3.Guaranteed by design.

TX_CLK

TXD[3:0]

tMTKHDX

tMTX

tMTXH

tMTXR

tMTXF

TX_EN

TX_ER

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