MPC8560CPX667JC datasheet(94/108 Pages) NXP

94 / 108 page

MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2

Freescale Semiconductor

System Design Information

When data is held high, SW1 is closed (SW2 is open) and RP is trimmed until the voltage at the pad equals

OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each

other in value. Then, Z0 = (RP + RN)/2.

Figure 59. Driver Impedance Measurement

The output impedance of the RapidIO port drivers targets 200-

Ω differential resistance. The value of this

resistance and the strength of the driver’s current source can be found by making two measurements. First,

the output voltage is measured while driving logic 1 without an external differential termination resistor.

The measured voltage is V1 = Rsource × Isource. Second, the output voltage is measured while driving logic

1 with an external precision differential termination resistor of value Rterm. The measured voltage is

V2 = 1/(1/R1 +1/R2)) × Isource. Solving for the output impedance gives Rsource = Rterm × (V1/V2 –1). The

drive current is then Isource =V1/Rsource.

Table 61 summarizes the signal impedance targets. The driver impedance are targeted at minimum VDD,

nominal OVDD, 105°C.

Table 61. Impedance Characteristics

Impedance

Local Bus, Ethernet, DUART, Control,

Configuration, Power Management

PCI/PCI-X

DDR DRAM

RapidIO

Symbol

Unit

43 Target

25 Target

20 Target

43 Target

25 Target

20 Target

Differential

200 Target

ZDIFF

Note: Nominal supply voltages. See Table 1, Tj = 105°C.

OVDD

OGND

Pad

Data

SW1

SW2

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