AS3911 datasheet(39/159 Pages) AMSCO

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ams Datasheet

Page 39

[v2-11] 2016-Jun-13

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AS3911 − Application Information

Serial Peripheral Interface (SPI)

While signal /SS is high the SPI interface is in reset, while it is

low the SPI interface is enabled. It is recommended to keep

signal /SS high whenever the SPI interface is not in use. MOSI is

sampled at the falling edge of SCLK. All communication is done

in blocks of 8 bits (bytes). First two bits of first byte transmitted

after high to low transition of /SS define SPI operation mode.

MSB bit is always transmitted first (valid for address and data).

Read and Write modes support address auto-incrementing,

which means that in case after the address and first data byte

some additional data bytes are sent (read), they are written to

(read from) addresses incremented by ‘1’. Figure 25 defines

possible modes.

MISO output is usually in tristate, it is only driven when output

data is available. Due to this the MOSI and the MISO can be

externally shorted to create a bidirectional signal.

During the time the MISO output is in tristate, it is possible to

switch on a 10k

Ω pull down by activating option bits miso_pd1

and miso_pd2 in the IO Configuration Register 2.

Figure 23:

Serial Data Interface (4-wire interface) Signal Lines

Figure 24:

Signal to Microcontroller

Name

Signal

Signal Level

Description

/SS

Digital input

CMOS

SPI Enable (active low)

MOSI

Digital input

CMOS

Serial data input

MISO

Digital output with

tristate

CMOS

Serial data output

SCLK

Digital input

CMOS

Clock for serial

communication

MOSI

MISO

MOSI

AS3911

MOSI

MISO

I/O

AS3911

Separate SPI Input and Output Signals to Microcontroller

Bidirectional Data IO Signal to Microcontroller

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