AS5013 datasheet(18/50 Pages) AMSCO

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AS5013 − Detailed Description

START condition and terminated with a STOP condition. The

number of data bytes transferred between START and STOP

conditions are not limited, and are determined by the master

device. The information is transferred byte-wise and each

receiver acknowledges with a ninth bit.

Acknowledge:

Each receiving device, when addressed, is obliged to generate

an acknowledge after the reception of each byte. The master

device must generate an extra clock pulse that is associated

with this acknowledge bit.

A device that acknowledges must pull down the SDA line during

the acknowledge clock pulse in such a way that the SDA line is

stable LOW during the HIGH period of the acknowledge-related

clock pulse. Of course, setup and hold times must be taken into

account. A master must signal an end of READ access to the

slave by not generating an acknowledge bit on the last byte

that has been clocked out of the slave. In this case, the slave

must leave the data line HIGH to enable the master to generate

the STOP condition.

Figure 17:

Data Read (Write Pointer, Then Read) - Slave Receive and Transmit

Depending upon the state of the R/W bit, two types of data

transfer are possible:

• Data transfer from a master transmitter to a slave

receiver: The first byte transmitted by the master is the

slave address, followed by R/W = 0. Next follows a number

of data bytes. The slave returns an acknowledge bit after

each received byte. If the slave does not understand the

command or data it sends a “not acknowledge”. Data is

transferred with the most significant bit (MSB) first.

• Data transfer from a slave transmitter to a master

receiver: The master transmits the first byte (the slave

address). The slave then returns an acknowledge bit,

followed by the slave transmitting a number of data bytes.

The master returns an acknowledge bit after all received

bytes other than the last byte. At the end of the last

received byte, a “not acknowledge” is returned. The

master device generates all of the serial clock pulses and

SDA

SCL

Start

Condition

Stop Condition or

Repeated Start Condition

MSB

R/W ACK

LSB

ACK

Slave Address

Repeated if more Bytes are transferred

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