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AS5013 데이터시트(PDF) 33 Page - ams AG

부품명 AS5013
상세설명  Low Power Integrated Hall IC for Human Interface Applications
PDF  50 Pages
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제조업체  AMSCO [ams AG]
홈페이지  http://www.ams.com
Logo AMSCO - ams AG

AS5013 데이터시트(HTML) 33 Page - ams AG

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ams Datasheet
Page 33
[v2-00] 2021-Apr-19
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AS5013 − I²C Registers
Hall Element Direct Read Registers (16h to 29h)
Each Hall element C1..C5 can be read independently, after each
interrupt (data ready).
One hall element value consists of two 12-bit signed-registers:
Cx_neg and Cx_pos. For each conversion cycle (i.e. after a
readout or Y_res in idle mode, or at each time-based conversion
cycle in Low Power mode), each Hall element is read twice: With
normal spin (result Cx_pos) and then with inverted spin (result
Cx_neg) in order to remove any Hall voltage offset from the Hall
elements.
The formula to read any Hall element Cx:
Cx = (Cx_pos – Cx_neg) / 2
Where
Cx_pos = (Cx_pos[11:8] << 8) | Cx_pos[7:0]
Cx_neg = (Cx_neg[11:8] << 8) | Cx_neg[7:0]
Figure 37:
Hall Element Direct Read Registers (2Ah)
The AGC register controls the sensitivity of each Hall element
C1...C5, in order to stay in the larger dynamic range of the 12-bit
ADC of the AS5013. In order to determine the best value to be
set during the AS5013 initialization, place your magnet on the
0,0 position (centered on C5 Hall element), and increase the
AGC value to obtain the nearest value to 2867 (= 70% of 4096).
It is possible that this value cannot be reached with small
magnets or with large airgaps. In that case set AGC to 3Fh, which
is the maximum sensitivity.
Power ON
The AS5013 has a Power ON Reset (POR) cell to monitor the VDD
voltage at startup and reset all the internal registers.
After the internal reset is completed, the POR cell is disabled in
order to save current during normal operation.
If VDD drops below 2.7V down to 0.2V, the POR cell will not be
enabled back, and the registers will not be correctly reseted or
can get random values.
Note: It is highly recommended to control the external RESETn
signal by applying a LOW pulse of >100ns once VDD reached
2.7V and VDDp reached 1.7V.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
AGC5
AGC4
AGC3
AGC2
AGC1
AGC0
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Reset value: 0010 0000
(EQ1)



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