PCF85363ATLSLASHA datasheet(85/86 Pages) NXP

85 / 86 page

NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I2C-bus

Contents

General description ............................................ 1

Features and benefits .........................................1

Applications .........................................................1

Ordering information .......................................... 2

4.1

Ordering options ................................................ 2

Block diagram ..................................................... 3

Pinning information ............................................ 4

6.1

Pinning ...............................................................4

6.2

Pin description ................................................... 5

Functional description ........................................5

7.1

Registers organization overview ........................6

7.1.1

Time mode registers ..........................................6

7.1.1.1

RTC mode time registers overview (RTCM

= 0) .................................................................... 7

7.1.1.2

Stop-watch mode time registers (RTCM =

1) ........................................................................8

7.1.2

Control registers overview ................................. 9

7.2

RTC mode time and date registers ..................10

7.2.1

Definition of BCD .............................................10

7.2.2

OS: Oscillator stop .......................................... 11

7.2.3

EMON: event monitor ......................................11

7.2.4

Definition of weekdays .....................................12

7.2.5

Definition of months .........................................12

7.2.6

Setting and reading the time in RTC mode ......12

7.3

Stop-watch mode time registers ...................... 14

7.3.1

Setting and reading the time in stop-watch

mode ................................................................14

7.4

Alarms ..............................................................15

7.4.1

Alarms in RTC mode .......................................15

7.4.1.1

Alarm1 and alarm2 registers in RTC mode ......15

7.4.1.2

Alarm1 and alarm2 control in RTC mode .........16

7.4.1.3

Alarm1 and alarm2 function in RTC mode .......17

7.4.2

Alarms in stop-watch mode ............................. 18

7.4.2.1

Alarm1 and alarm2 registers in stop-watch

mode ................................................................18

7.4.2.2

Alarm1 and alarm2 control in stop-watch

mode ................................................................19

7.4.2.3

Alarm1 and alarm2 function in stop-watch

mode ................................................................20

7.4.3

Alarm interrupts ............................................... 21

7.5

WatchDog ........................................................ 22

7.5.1

WatchDog functions .........................................22

7.5.1.1

WatchDog repeat mode ...................................23

7.5.1.2

WatchDog single shot mode ............................23

7.5.1.3

WatchDog interrupts ........................................ 24

7.6

Single RAM byte ..............................................24

7.7

Timestamps ......................................................24

7.7.1

Timestamps interrupts ..................................... 29

7.8

Offset register .................................................. 29

7.8.1

Correction when OFFM = 0 .............................30

7.8.2

Correction when OFFM = 1 .............................31

7.8.3

Offset calibration workflow ...............................31

7.8.4

Offset interrupts ............................................... 33

7.9

Interrupts ..........................................................33

7.9.1

ILPA/ILPB: interrupt level or pulse mode ......... 34

7.9.2

Interrupt enable bits .........................................35

7.10

Oscillator register .............................................37

7.10.1

CLKIV: invert the clock output ......................... 37

7.10.2

OFFM: offset calibration mode ........................ 37

7.10.3

12_24: 12 hour or 24 hour clock ......................37

7.10.4

LOWJ: low jitter mode ..................................... 37

7.10.5

OSCD[1:0]: quartz oscillator drive control ........38

7.10.6

CL[1:0]: quartz oscillator load capacitance ...... 38

7.11

Battery switch register ..................................... 39

7.11.1

BSOFF: battery switch on/off control ............... 39

7.11.2

BSRR: battery switch internal refresh rate .......40

7.11.3

BSM[1:0]: battery switch mode ........................40

7.11.3.1 Switching at the Vth level, BSM[1:0] = 00 ........41

7.11.3.2 Switching at the VBAT level, BSM[1:0] = 01 .... 42

7.11.3.3 Switching at the higher of VBAT or Vth

level, BSM[1:0] = 10 ........................................42

7.11.3.4 Switching at the lower of VBAT and Vth

level, BSM[1:0] = 11 ........................................ 43

7.11.4

BSTH: threshold voltage control ......................44

7.11.5

Battery switch interrupts .................................. 44

7.12

Pin_IO register .................................................44

7.12.1

CLKPM: CLK pin mode control ........................44

7.12.2

TSPULL: TS pin pull-up resistor value .............45

7.12.3

TSL: TS pin level sense .................................. 45

7.12.4

TSPM[1:0]: TS pin I/O control ......................... 45

7.12.4.1 TS pin output mode; INTB ...............................46

7.12.4.2 TS pin output mode; CLK ................................46

7.12.4.3 TS pin disabled ................................................46

7.12.5

TSIM: TS pin input type control ....................... 46

7.12.5.1 TS pin input mode ...........................................47

7.12.6

INTAPM[1:0]: INTA pin mode control ............... 47

7.12.6.1 INTAPM[1:0]: INTA .......................................... 47

7.12.6.2 INTAPM[1:0]: clock data .................................. 47

7.12.6.3 INTAPM[1:0]: battery mode indication ............. 48

7.13

Function register ..............................................48

7.13.1

100TH: 100th seconds mode .......................... 48

7.13.2

PI[1:0]: Periodic interrupt ................................. 48

7.13.3

RTCM: RTC mode ...........................................49

7.13.4

STOPM: STOP mode control .......................... 49

7.13.5

COF[2:0]: Clock output frequency ................... 50

7.14

Flags register ...................................................51

7.15

Reset register .................................................. 52

7.15.1

SR - Software reset .........................................52

7.15.2

CPR: clear prescaler ....................................... 55

7.15.3

CTS: clear timestamp ......................................55

7.16

Stop_enable register ........................................55

7.17

64 byte RAM ................................................... 57

I2C-bus interface ...............................................57

8.1

Bit transfer ....................................................... 58

8.2

START and STOP conditions .......................... 58

8.3

Acknowledge ....................................................58

Interface protocol ..............................................59

9.1

Write protocol ...................................................59

9.2

Read protocol .................................................. 59

9.3

Slave addressing ............................................. 59

9.3.1

Slave address ..................................................60

Application design-in information ...................60

PCF85363A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3.1 — 18 June 2021

85 / 86

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