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ES9219C 데이터시트(PDF) 39 Page - ESS Technology,Inc

부품명 ES9219C
상세설명  32-bit Stereo Low Power DAC with Headphone Amplifier, Analog Volume Control, and Output Switch
PDF  67 Pages
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제조업체  ESS [ESS Technology,Inc]
홈페이지  http://www.esstech.com
Logo ESS - ESS Technology,Inc

ES9219C 데이터시트(HTML) 39 Page - ESS Technology,Inc

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ES9219 Datasheet
CONFIDENTIAL ADVANCE INFORMATION 1.0.4
February 27, 2020
39
ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-8800 • Fax (408) 643-8801
Register 10: MASTER MODE AND SYNC CONFIGURATION
I2C Slave Access:
I2S Sync Slave Access:
Clock Domain:
Bits
[7]
[6:5]
[4]
[3:0]
Mnemonic
MASTER_MODE
MASTER_DIV
128fs_MODE
LOCK_SPEED
Bits
Mnemonic
Description
[7]
MASTER_MODE
Enables master mode which causes the Sabre to drive the DATA_CLK and DATA1 signals when in I2S mode
Can also be enabled when in DSD mode to enable DATA_CLK only.
1’b0: Disables master mode (default).
1’b1: Enables master mode.
[6:5]
MASTER_DIV
Sets the frame clock (DATA1) and DATA_CLK frequencies when in master mode.
This register is used when in normal synchronous operation.
2’b00: DATA_CLK frequency = MCLK/2 (default).
2’b01: DATA_CLK frequency = MCLK/4.
2’b10: DATA_CLK frequency = MCLK/8.
2’b11: DATA_CLK frequency = MCLK/16.
[4]
128fs_MODE
Enables operation of the DAC while in synchronous mode with a 128*fs MCLK.
1’b0: Disables MCLK = 128*fs mode (default).
1’b1: Enables MCLK = 128*fs mode.
[3:0]
LOCK_SPEED
Sets the number of audio samples required before the DPLL and ASRC lock to the incoming signal.
More audio samples give a better initial estimate of the MCLK/FS ratio at the expense of a longer locking
interval.
4’d0: 16384 FS edges
4’d1: 8192 FS edges
4’d2: 5461 FS edges (default)
4’d3: 4096 FS edges
4’d4: 3276 FS edges
4’d5: 2730 FS edges
4’d6: 2340 FS edges
4’d7: 2048 FS edges
4’d8: 1820 FS edges
4’d9: 1638 FS edges
4’d10: 1489 FS edges
4’d11: 1365 FS edges
4’d12: 1260 FS edges
4’d13: 1170 FS edges
4’d14: 1092 FS edges
4’d15: 1024 FS edges
Register 11: OVERCURRENT PROTECTION
I2C Slave Access:
I2S Sync Slave Access:
Clock Domain:
Bits
[7]
[6:4]
[3:0]
Mnemonic
OC_SD_EN
OC_SD_GAIN
RESERVED
Bits
Mnemonic
Description
[7]
OC_SD_EN
Enable an automatic detection circuit to mute the DAC (and disable the headphone amplifier) when an overcurrent
event is detected.
1’b0: Automatic overcurrent shutdown is disabled (default).



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