STSPIN32G4 datasheet(47/48 Pages) STMICROELECTRONICS

47 / 48 page

List of figures

Figure 1.

STSPIN32G4 system-in-package block diagram ............................................. 3

Figure 2.

Gate driver block diagram ............................................................ 4

Figure 3.

STSPIN32G4 pin connection ......................................................... 11

Figure 4.

Power-up sequence (REGIN shorted with VCC) ............................................ 15

Figure 5.

VCC Buck configuration............................................................. 16

Figure 6.

VCC buck regulator soft-start ......................................................... 16

Figure 7.

VCC externally supplied (buck disabled) ................................................. 17

Figure 8.

VCC buck regulator short-circuit protection................................................ 17

Figure 9.

3.3 V LDO regulator supplied through VCC ............................................... 18

Figure 10.

3.3 V LDO regulator supplied through VCC (external resistor)................................... 18

Figure 11.

3.3 V LDO regulator with external supply ................................................. 18

Figure 12.

3.3 V externally supplied (linear regulator disabled) .......................................... 19

Figure 13.

Standby regulator enabled ........................................................... 19

Figure 14.

Gate driver block diagram ........................................................... 20

Figure 15.

Deadtime timing (with interlocking enabled) ............................................... 21

Figure 16.

Low-side gate driver output characteristic in UVLO range...................................... 21

Figure 17.

High-side gate driver output characteristic in UVLO range ..................................... 21

Figure 18.

External bootstrap diode configuration ................................................... 23

Figure 19.

VDS monitoring protection timings...................................................... 24

Figure 20.

Standby timings .................................................................. 28

Figure 21.

FAULT clearing via input lines......................................................... 29

Figure 22.

ESD protection strategy ............................................................. 34

Figure 23.

Application example ............................................................... 36

Figure 24.

VFQFPN 9X9X1.0 64 PITCH 0.50 package outline .......................................... 38

Figure 25.

VFQFPN 9X9X1.0 64 PITCH 0.50 suggested footprint........................................ 39

Figure 26.

Standby current ISTBY vs. temperature (normalized at ambient temperature)......................... 40

Figure 27.

Standby current ISTBY vs. supply voltage VM (normalized at VM = 75V) ............................ 40

Figure 28.

VCC quiescent consumption vs. temperature (normalized at ambient temperature) .................... 40

STSPIN32G4

List of figures

DS13630 - Rev 1

page 47/48

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