W7100A datasheet(8/160 Pages) WIZNET

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W7100A Datasheet v1.2.5

Figure 5.8 Timer/Counter0, Mode2: 8-Bit Timer/Counter with Auto-Reload...................... 56

Figure 5.9 Timer/Counter0, Mode3: Two 8-Bit Timers/Counters .................................... 56

Figure 5.10 Timer/Counter1, Mode0: 13-Bit Timer/Counter......................................... 57

Figure 5.11 Timer/Counter1, Mode1: 16-Bit Timers/Counters ...................................... 57

Figure 5.12 Timer/Counter1, Mode2: 8-Bit Timer/Counter with Auto-Reload .................... 58

Figure 5.13 Timer2 Configuration Register .............................................................. 59

Figure 5.14 Timer/Counter2, 16-Bit Timer/Counter with Auto-Reload ............................ 60

Figure 5.15 Interrupt Enable Register — Timer2 ....................................................... 60

Figure 5.16 Interrupt Priority Register — Timer2....................................................... 61

Figure 5.17 Timer2 Configuration Register — TF2...................................................... 61

Figure 5.18 Timer/Counter2, 16-Bit Timer/Counter with Capture Mode .......................... 61

Figure 5.19 Timer2 for Baud Rate Generator Mode.................................................... 62

Figure 6.1 UART Buffer Register........................................................................... 63

Figure 6.2 UART Configuration Register ................................................................. 63

Figure 6.3 UART Bits in Power Configuration Register ................................................ 64

Figure 6.4 UART Bits in Interrupt Enable Register ..................................................... 65

Figure 6.5 UART Bits in Interrupt Priority Register..................................................... 65

Figure 6.6 UART Configuration Register ................................................................. 65

Figure 6.7 Timing Diagram for UART Transmission Mode0 (clk = 88.4736 MHz) ................... 66

Figure 6.8 Timing Diagram for UART Transmission Mode1 ............................................ 66

Figure 6.9 Timing Diagram for UART Transmission Mode2 ............................................ 66

Figure 6.10 Timing Diagram for UART Transmission Mode3........................................... 67

Figure 7.1 Watchdog Timer Structure .................................................................... 68

Figure 7.2 Interrupt Enable Register ..................................................................... 68

Figure 7.3 Extended Interrupt Enable Register ......................................................... 68

Figure 7.4 Extended interrupt Priority Register ........................................................ 69

Figure 7.5 Watchdog Control Register.................................................................... 69

Figure 7.6 Watchdog Control Register.................................................................... 71

Figure 7.7 Clock Control register – Watchdog bits ..................................................... 72

Figure 8.1 TCPIPCore Memory Map ....................................................................... 73

Figure 8.2 SOCKET n Status transition ..................................................................100

Figure 8.3 Calculate Physical Address ...................................................................107

Figure 9.1 Allocation Internal TX/RX memory of SOCKET n .........................................114

Figure 9.2 TCP SERVER & TCP CLIENT ...................................................................115

Figure 9.3 “TCP SERVER” Operation Flow ..............................................................116

Figure 9.4 “TCP CLIENT” Operation Flow ..............................................................123

Figure 9.5 UDP Operation Flow...........................................................................124

Figure 9.6 The received UDP data format ..............................................................126

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