ADIN2111CCPZ-R7 datasheet(64/125 Pages) AD

64 / 125 page

Data Sheet

ADIN2111

REGISTERS

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Rev. 0 | 64 of 125

Table 65. Bit Descriptions for TX_PRI

Bits

Bit Name

Description

Reset

Access

101: 100/0 host/port. The host is always guaranteed access to wire.

110: 0/100 host/port. Port to port traffic always gets priority.

MAC FIFO Clear Register

Address: 0x36, Reset: 0x00000000, Name: FIFO_CLR

Table 66. Bit Descriptions for FIFO_CLR

Bits

Bit Name

Description

Reset

Access

[31:4]

RESERVED

Reserved.

0x0

LES_P2P_FIFOS_CLR

Clear the Port to Port FIFOs on LES. If a frame is being transmitted from a Tx FIFO, transmission

stops and a bad CRC is appended to the frame. Writes to Rx FIFOs resume at the start of the next

received frame.

0x0

LES_FIFOS_CLR

Clear All FIFOs. If a frame is being transmitted from a Tx FIFO, transmission stops and a bad CRC

is appended to the frame. Writes to Rx FIFOs resume at the start of the next received frame.

0x0

RESERVED

Reserved.

0x0

MAC_RXF_CLR

Clear the Receive FIFOs. Writes to the Rx FIFOs resume at the start of the next frame.

0x0

Scratch Registers

Address: 0x37 to 0x3A (Increments of 1), Reset: 0x00000000, Name: SCRATCHn

Table 67. Bit Descriptions for SCRATCHn

Bits

Bit Name

Description

Reset

Access

[31:0]

SCRATCH_DATA

Scratch Data.

0x0

R/W

MAC Reset Status Register

Address: 0x3B, Reset: 0x00000003, Name: MAC_RST_STATUS

If this register returns 0x00000000_00000001 when read, the oscillator clock is active but the 25 MHz crystal clock is not active.

If this register returns 0x00000000_00000003 when read, both the oscillator clock and the 25 MHz crystal clock are active.

If this register returns 0x00000000_00000000 (SDO output pad is enabled as CS is low), the SPI slave and MAC core are both still in reset.

Only single SPI reads of this register are supported. An SPI burst read must not increment into this register.

Table 68. Bit Descriptions for MAC_RST_STATUS

Bits

Bit Name

Description

Reset

Access

[31:2]

RESERVED

Reserved.

0x0

MAC_CRYSL_CLK_RDY

MAC Crystal Clock Ready. If 0, this field indicates that the MAC core has released from reset.

If 1, this field indicates that the MAC core released from reset. The MAC core is released from

reset when the crystal clock (25 MHz) is ready.

0x1

MAC_OSC_CLK_RDY

MAC Oscillator Clock Ready.

0x1

Software Reset Register

Address: 0x3C, Reset: 0x00000000, Name: SOFT_RST

ADIN2111CCPZ-R7 데이터시트(PDF) 64 Page - Analog Devices

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