DLPC4430ZPC datasheet(34/49 Pages) TI

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9 Power Supply Recommendations

9.1 System Power Regulations

It is strongly recommended that the VDD18_PLLD, VDD18_PLLM1, and VDD18_PLLM2 power feeding internal

PLLs be derived from an isolated linear regulator in order to minimize the AC Noise component. The

VDD11_PLLD, VDD11_PLLM1, VDD11_PLLM2, and VDD11_PLLS can be derived from the same regulator

as the core VDD11, but they have to be filtered.

9.2 System Power-Up Sequence

Although the DLPC4430 controller requires an array of power supply voltages (1.15V, 1.8V, 3.3V), there

are no restrictions regarding the relative order of power supply sequencing for both power-up and power-

down scenarios. Similarly, there is no minimum time between powering-up or powering-down the different

supplies feeding the DLP controller. However, note that it is not uncommon for there to be power sequencing

requirements for the devices that share the supplies with the DLP controller.

• 1.15V core power is applied whenever any I/O power is applied to ensures the state of the associated I/O

that are powered are controlled to a known state. Thus, it is recommended to apply core power first. Other

supplies are applied only after the 1.1V core has ramped up.

• All DLPC4430 device power must be applied before POSENSE is asserted to ensure proper power-up

initialization.

Typically the DLPC4430 controller power-up sequencing is handled by external hardware. An external power

monitor will hold the controller in system reset during power-up (i.e. POSENSE = 0). During this time all DLP

controller I/Os are tri-stated. The primary PLL (PLLM1) is released from reset upon the low to high transition of

POSENSE but the controller keeps the rest of the device in reset for an additional 60 ms to allow the PLL to lock

and stabilize its outputs. After this 60 ms delay the ARM-9 related internal resets are de-asserted causing the

microprocessor to begin its boot-up routine.

Figure 9-1. System Power-Up Sequence

9.3 Power-On Sense (POSENSE) Support

In order to set up the power monitor to trip within the DLPC4430 controller minimum supply voltage

specifications, it is recommended that the external power monitor generating POSENSE targets its threshold

to 90% of the minimum supply voltage specifications and ensures that POSENSE remains low a sufficient

amount of time for all supply voltages to reach minimum device requirements and stabilize. Note that the trip

DLPC4430

DLPS223 – DECEMBER 2021

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DLPC4430ZPC 데이터시트(PDF) 34 Page - Texas Instruments