6.13 Programmable Output Clocks Switching Characteristics

PARAMETER

TEST CONDITIONS

TO (OUTPUT)

MIN

MAX

UNIT

Clock frequency, OCLKA(1)

OCLKA

0.787

50

MHz

Cycle Time, OCLKA

OCLKA

20

1270.6

ns

Pulse Duration, high(2)

50% to 50% reference points

(signal)

OCLKA

ns

Pulse Duration, low(2)

50% to 50% reference points

(signal)

OCLKA

ns

Jitter

OCLKA

350

ps

Clock frequency, OCLKB(1)

OCLKB

0.787

50

MHz

Cycle Time, OCLKB

OCLKB

20

1270.6

ns

Pulse Duration, high(2)

50% to 50% reference points

(signal)

OCLKB

ns

Pulse Duration, low(2)

50% to 50% reference points

(signal)

OCLKB

ns

Jitter

OCLKB

350

ps

Clock frequency, OCLKC(1)

OCLKC

0.787

50

MHz

Cycle Time, OCLKC(2)

OCLKC

20

1270.6

ns

Pulse Duration, high

50% to 50% reference points

(signal)

OCLKC

ns

Pulse Duration, low(2)

50% to 50% reference points

(signal)

OCLKC

ns

Jitter

OCLKC

350

ps

(1)

The frequency of OCLKA thru OCLKC is programmable.

(2)

The Duty Cycle of OCLKA thru OCLKC is within +/- 2 ns of 50%.

6.14 Synchronous Serial Port Interface (SSP) Switching Characteristics

PARAMETER

TEST CONDITIONS

FROM (INPUT)

TO (OUTPUT)

MIN

MAX

UNIT

Clock Frequency,

SSPx_CLK

N/A

SSPx_CLK

73

25000

kHz

Cycle time, SSPx_CLK

N/A

SSPx_CLK

0.040

13.6

µs

Pulse Duration, high

50% to 50% reference

points (signal)

N/A

SSPx_CLK

40%

Pulse Duration, low

50% to 50% reference

points (signal)

N/A

SSPx_CLK

40%

SSP Primary (1)

Output Propagation, Clock

to Q, SSPx_DO(2)

SSPx_CLK↓

SSPx_DO

-5

5

ns

Output Propagation, Clock

to Q, SSPx_DO(2)

SSPx_CLK↑

SSPx_DO

-5

5

ns

SSP Secondary (1)

Output Propagation, Clock

to Q, SSPx_DO(2)

SSPx_CLK↓

SSPx_DO

0

34

ns

Output Propagation, Clock

to Q, SSPx_DO(2)

SSPx_CLK↑

SSPx_DO

0

34

ns

(1)

The SSP can be used as an SSP Primary, or as an SSP Secondary. When used as a Primary, the SSP can be configured to sample DI

with the same internal clock edge used to transmit the next DO, which provides a full cycle rather than a half cycle timing path, allowing

operation at higher SPI clock frequencies.

(2)

The SSP can be configured into four different operational modes/configurations.

DLPC4430

DLPS223 – DECEMBER 2021

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