UCS2113 datasheet(41/62 Pages) MICROCHIP

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DS20005680B-page 41

UCS2113

8.3

Configuration Registers

The Configuration registers control basic device

functionality. The contents of these registers are

retained in Sleep.

GENERAL CONFIGURATION 1 REGISTER (ADDRESS 11H)

R/W-0

U-0

R/W-0

R/W-1

U-1

U-0

ALERT1_MASK

—

DSCHG1

PWR_EN1S

DISCHG_TIME<1:0>

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit

C = Clear on Read

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

ALERT1_MASK: Mask errors for all interrupts in Register 8-3 except OV_LIM1 and TSD.

1 = The ALERT#1 pin will only assert if a OV_LIM1 or TSD is detected

0 = The ALERT#1 pin will be asserted if an error condition or indicator event is detected

bit 6

Unimplemented

bit 5

DSCHG1: Forces the VBUS1 to be reset and discharged when the UCS2113 is in the Active state

and the EN_VBUS_DISCHG bit is logic '1'. Writing this bit to a logic ‘1’ will cause the port power

switch to be opened and the discharge circuitry to activate and discharge VBUS. Actual discharge

time is controlled by DISCHG_TIME<1:0>. This bit must be cleared by the SMBus host after the

forced VBUS discharge.

1 =VBUS1 discharge initiated

0 = Port 1 not in discharge

bit 4

PWR_EN1S: Power Enable Port 1 override - This bit is OR’ed with the PWR_EN1 pin. Thus, if the

polarity is set to active-high, either the PWR_EN1 pin or this bit must be ‘1’ to enable the port power

switch.

bit 3-2

DISCHG_TIME<1:0>: Discharge time Port 1 - sets tDISCHARGE. The discharge time value is the

same for both ports.

00 = 100 ms

01 = 200 ms

10 = 300 ms

11 = 400 ms

bit 1-0

Unimplemented

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