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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STM32F469AE 데이터시트(PDF) 183 Page - STMicroelectronics |
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STM32F469AE 데이터시트(HTML) 183 Page - STMicroelectronics |
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183 / 220 page  DS11189 Rev 7 183/220 STM32F469xx Electrical characteristics 191 Figure 72. SDRAM write access waveforms Table 103. LPSDR SDRAM read timings(1) 1. Guaranteed based on test during characterization. Symbol Parameter Min Max Unit tW(SDCLK) FMC_SDCLK period 2THCLK − 0.5 2THCLK+0.5 ns tsu(SDCLKH_Data) Data input setup time 2.5 - th(SDCLKH_Data) Data input hold time 0 - td(SDCLKL_Add) Address valid time - 1 td(SDCLKL_SDNE) Chip select valid time - 1 th(SDCLKL_SDNE) Chip select hold time 1 - td(SDCLKL_SDNRAS SDNRAS valid time - 1 th(SDCLKL_SDNRAS) SDNRAS hold time 1 - td(SDCLKL_SDNCAS) SDNCAS valid time - 1 th(SDCLKL_SDNCAS) SDNCAS hold time 1 - MS32752V2 Row n Col1 FMC_SDCLK FMC_A[12:0] FMC_SDNRAS FMC_SDNCAS FMC_SDNWE FMC_D[31:0] FMC_SDNE[1:0] td(SDCLKL_AddR) td(SDCLKL_AddC) th(SDCLKL_AddR) th(SDCLKL_AddC) td(SDCLKL_SNDE) td(SDCLKL_Data) th(SDCLKL_Data) Col2 Coli Coln Data2 Datai Datan Data1 th(SDCLKL_SNDE) td(SDCLKL_NRAS) td(SDCLKL_NCAS) th(SDCLKL_NCAS) th(SDCLKL_NRAS) td(SDCLKL_NWE) th(SDCLKL_NWE) FMC_NBL[3:0] td(SDCLKL_NBL) |
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