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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STM32F732IE 데이터시트(PDF) 157 Page - STMicroelectronics |
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STM32F732IE 데이터시트(HTML) 157 Page - STMicroelectronics |
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157 / 226 page  DS11854 Rev 6 157/226 STM32F732xx STM32F733xx Electrical characteristics 198 General PCB design guidelines Power supply decoupling should be performed as shown in Figure 48 or Figure 49, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 48. Power supply and reference decoupling (VREF+ not connected to VDDA) 1. VREF+ input is available on all the packages except LQFP64, whereas the VREF– is available only on UFBGA176 and UFBGA144. When VREF- is not available, it is internally connected to VSSA. Figure 49. Power supply and reference decoupling (VREF+ connected to VDDA) 1. VREF+ input is available on all the packages except LQFP64, whereas the VREF– is available only on UFBGA176 and UFBGA144. When VREF- is not available, it is internally connected to VSSA. STM32 1 μF // 10 nF 1 μF // 10 nF VREF+ (1) VDDA VSSA/VREF+ (1) ai17535c STM32F 1 μF // 10 nF ai17536c VREF+/VDDA VREF-/VSSA (1) (1) |
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