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STM32F732IE 데이터시트(PDF) 181 Page - STMicroelectronics

부품명 STM32F732IE
상세설명  Arm® Cortex®-M7 32b MCUFPU, 462DMIPS, up to 512KB Flash 256164KB RAM, USB OTG HS/FS, 18 TIMs, 3 ADCs, 21 com IF
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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STM32F732IE 데이터시트(HTML) 181 Page - STMicroelectronics

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DS11854 Rev 6
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STM32F732xx STM32F733xx
Electrical characteristics
198
Synchronous waveforms and timings
Figure 64 through Figure 67 represent synchronous waveforms and Table 101 through
Table 104 provide the corresponding timings. The results shown in these tables are
obtained with the following FMC configuration:
•
BurstAccessMode = FMC_BurstAccessMode_Enable;
•
MemoryType = FMC_MemoryType_CRAM;
•
WriteBurst = FMC_WriteBurst_Enable;
•
CLKDivision = 1;
•
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
•
CL = 30 pF on data and address lines. CL = 10 pF on FMC_CLK unless otherwise
specified.
In all timing tables, the THCLK is the HCLK clock period.
–For 2.7 V≤ VDD≤ 3.6 V, maximum FMC_CLK = 108 MHz at CL=20 pF or 90 MHz at
CL=30 pF (on FMC_CLK).
–For 1.71 V≤ VDD<2.7 V, maximum FMC_CLK = 70 MHz at CL=10 pF (on FMC_CLK).
1. Guaranteed by characterization results.
Table 100. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)
1. Guaranteed by characterization results.
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
9Thclk - 1
9Thclk + 1
ns
tw(NWE)
FMC_NWE low time
7Thclk -0.5
7Thclk + 0.5
tsu(NWAIT_NE)
FMC_NWAIT valid before FMC_NEx high
6Thclk + 2
-
th(NE_NWAIT)
FMC_NEx hold time after FMC_NWAIT
invalid
4Thclk - 1
-



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