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STM32WL55JC 데이터시트(PDF) 97 Page - STMicroelectronics

부품명 STM32WL55JC
상세설명  Multiprotocol LPWAN dual core 32-bit Arm® Cortex®-M4/M0 LoRa®, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM
PDF  147 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
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STM32WL55JC 데이터시트(HTML) 97 Page - STMicroelectronics

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DS13293 Rev 2
97/147
STM32WL55/54xx
Electrical characteristics
137
5.3.8
Wakeup time from low-power modes and voltage scaling
transition times
The wakeup times given in the table below, are the latency between the event and the
execution of the first user instruction.
The device goes in low-power mode after the WFE (wait for event) instruction.
APB1
I2C3 independent clock domain
2.29
1.87
1.30
µA/MHz
LPTIM1
1.67
1.44
1.50
LPTIM1 independent clock domain
2.50
2.19
1.45
LPTIM2
1.67
1.37
0.90
LPTIM2 independent clock domain
2.50
2.12
1.55
LPTIM3
0.83
0.69
0.65
LPTIM3 independent clock domain
2.29
1.94
0.65
LPUART1
2.08
1.81
3.55
LPUART1 independent clock
domain
2.50
2.06
1.35
RTCAPB
2.08
1.81
1.50
SPI2
1.46
1.19
0.90
TIM2
4.58
3.81
2.95
USART2
1.88
1.56
1.35
USART2 independent clock domain
4.58
3.75
3.05
WWDG1
0.42
0.31
0.05
All APB1 peripherals(1)
19.6
16.1
20.2
APB2
ADC
1.25
1.00
0.70
µA/MHz
ADC independent clock domain
0.21
0.13
0.30
SPI1
1.25
1.06
0.90
TIM1
6.25
5.19
8.30
TIM16
2.29
1.94
1.35
TIM17
2.29
1.87
1.25
USART1
1.67
1.38
1.00
USART1 independent clock domain
4.17
3.38
2.90
All APB2 peripherals(1)
15.8
13.0
15.8
APB3
SUBGHZSPI
1.46
1.25
1.10
µA/MHz
All APB3 peripherals
1.46
1.25
1.10
All peripherals(1)
62.9
52.3
59.7
1. Without independent clocks.
Table 56. Peripheral current consumption (continued)
Peripheral
Range 1
Range 2
LPRun and LPSleep
Unit



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