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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AD9161BBCZ 데이터시트(PDF) 47 Page - Analog Devices |
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AD9161BBCZ 데이터시트(HTML) 47 Page - Analog Devices |
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47 / 144 page  Data Sheet AD9161/AD9162 Rev. D | Page 47 of 144 Table 17. Data Structure per Lane for JESD204B Operating Modes1 JESD204B Parameters Lane No. Frame 0 Frame 1 Frame 2 Frame 3 L = 8, M = 1, F = 1, S = 4 Lane 0 M0S0[15:8] Lane 1 M0S0[7:0] Lane 2 M0S1[15:8] Lane 3 M0S1[7:0] Lane 4 M0S2[15:8] Lane 5 M0S2[7:0] Lane 6 M0S3[15:8] Lane 7 M0S3[7:0] L = 8, M = 2, F = 1, S = 2 Lane 0 M0S0[15:8] Lane 1 M0S0[7:0] Lane 2 M0S1[15:8] Lane 3 M0S1[7:0] Lane 4 M1S0[15:8] Lane 5 M1S0[7:0] Lane 6 M1S1[15:8] Lane 7 M1S1[7:0] L = 6, M = 2, F = 2, S = 3 Lane 0 M0S0[15:8] M0S0[7:0] Lane 1 M0S1[15:8] M0S1[7:0] Lane 2 M0S2[15:8] M0S2[7:0] Lane 3 M1S0[15:8] M1S0[7:0] Lane 4 M1S1[15:8] M1S1[7:0] Lane 5 M1S2[15:8] M1S2[7:0] L = 4, M = 2, F = 1, S = 1 Lane 0 M0S0[15:8] Lane 1 M0S0[7:0] Lane 2 M1S0[15:8] Lane 3 M1S0[7:0] L = 3, M = 2, F = 4, S = 3 Lane 0 M0S0[15:8] M0S0[7:0] M0S1[15:8] M0S1[7:0] Lane 1 M0S2[15:8] M0S2[7:0] M1S0[15:8] M1S0[7:0] Lane 2 M1S1[15:8] M1S1[7:0] M1S2[15:8] M1S2[7:0] L = 2, M = 2, F = 2, S = 1 Lane 0 M0S0[15:8] M0S0[7:0] Lane 1 M1S0[15:8] M1S0[7:0] L = 1, M = 2, F = 4, S = 1 Lane 0 M0S0[15:8] M0S0[7:0] M1S0[15:8] M1S0[7:0] 1 Mx is the converter number and Sy is the sample number. For example, M0S0 means Converter 0, Sample 0. Blank cells are not applicable. PHYSICAL LAYER The physical layer of the JESD204B interface, hereafter referred to as the deserializer, has eight identical channels. Each channel consists of the terminators, an equalizer, a clock and data recovery (CDR) circuit, and the 1:40 demux function (see Figure 144). EQUALIZER CDR 1:40 DESERIALIZER FROM SERDES PLL SPI CONTROL TERMINATION SERDINx± Figure 144. Deserializer Block Diagram JESD204B data is input to the AD9161/AD9162 via the SERDINx± 1.2 V differential input pins as per the JESD204B specification. Interface Power-Up and Input Termination Before using the JESD204B interface, it must be powered up by setting Register 0x200, Bit 0 = 0. In addition, each physical lane (PHY) that is not being used (SERDINx±) must be powered down. To do so, set the corresponding Bit x for Physical Lane x in Register 0x201 to 0 if the physical lane is being used, and to 1 if it is not being used. The AD9161/AD9162 autocalibrate the input termination to 50 Ω. Before running the termination calibration, Register 0x2A7 and Register 0x2AE must be written as described in Table 18 to guarantee proper calibration. The termination calibration begins when Register 0x2A7, Bit 0 and Register 0x2AE, Bit 0 transition from low to high. Register 0x2A7 controls autocalibration for |
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