AD9161BBCZ datasheet(113/144 Pages) AD

113 / 144 page

Data Sheet

AD9161/AD9162

Rev. D | Page 113 of 144

Hex.

Addr. Name

Bits Bit Name

Settings

Description

Reset

Access

0100 Sample 4.

0101 Sample 5.

0110 Sample 6.

0111 Sample 7.

1000 Sample 8.

1001 Sample 9.

1010 Sample 10.

1011 Sample 11.

1100 Sample 12.

1101 Sample 13.

1110 Sample 14.

1111 Sample 15.

[3:2] SHORT_TPL_M_SEL

Short transport layer test DAC

selection. Select which DAC to

check.

0x0

R/W

00 DAC 0.

01 DAC 1.

10 DAC 2.

11 DAC 3.

SHORT_TPL_TEST_RESET

Short transport layer test reset.

Resets the result of short

transport layer test.

0x0

R/W

0 Not reset.

1 Reset.

SHORT_TPL_TEST_EN

Short transport layer test

enable. Enable short transport

layer test.

0x0

R/W

0 Disable.

1 Enable.

0x32D SHORT_TPL_TEST_1

[7:0] SHORT_TPL_REF_SP_LSB

Short transport layer reference

sample LSB. This is the lower

eight bits of expected DAC

sample. It is used to compare

with the received DAC sample

at the output of JESD204B Rx.

0x0

R/W

0x32E SHORT_TPL_TEST_2

[7:0] SHORT_TPL_REF_SP_MSB

Short transport layer test

reference sample MSB. This is

the upper eight bits of

expected DAC sample. It is used

to compare with the received

sample at JESD204B Rx output.

0x0

R/W

0x32F SHORT_TPL_TEST_3

[7:1] RESERVED

Reserved.

0x0

SHORT_TPL_FAIL

Short transport layer test fail.

This bit shows if the selected

DAC sample matches the

reference sample. If they match,

the test passes; otherwise, the

test fails.

0x0

0 Test pass.

1 Test fail.

0x334 JESD_BIT_INVERSE_CTRL

[7:0] JESD_BIT_INVERSE

Each bit of this byte inverses

the JESD204B deserialized data

from one specific JESD204B Rx

PHY. The bit order matches the

logical lane order. For example,

Bit 0 controls Lane 0, Bit 1

controls Lane 1.

0x0

R/W

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