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MPC5675KFF0VMS2R 데이터시트(PDF) 28 Page - NXP Semiconductors

부품명 MPC5675KFF0VMS2R
상세설명  MPC5675K Microcontroller
PDF  147 Pages
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제조업체  NXP [NXP Semiconductors]
홈페이지  http://www.nxp.com
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MPC5675KFF0VMS2R 데이터시트(HTML) 28 Page - NXP Semiconductors

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MPC5675K Microcontroller Data Sheet, Rev. 9
Package pinouts and signal descriptions
NXP Semiconductors
28
D10
JCOMP
pulldown
not available
GP Slow
VDD_HV_IO
E1
Nexus MDO[0]1
—
not available
GP Slow/Fast
VDD_HV_IO
E4
NMI
pullup
not available
GP Slow
VDD_HV_IO
R232
dramc CLKB
—
—
DRAM CLK
VDD_HV_DRAM
T232
dramc CLK
disabled
—
DRAM CLK
VDD_HV_DRAM
W1
XTALIN
—
not available
Analog Feedthrough
VDD_HV_IO
Y2
RESET
pulldown
not available
Reset
VDD_HV_IO
Y19
TCK3
pullup
not available
GP Slow
VDD_HV_IO
AA1
XTALOUT
—
not available
Analog Feedthrough
VDD_HV_IO
AA2
FCCU_F[0]
disabled
not available
GP Slow/Medium
VDD_HV_IO
AB19
TMS
pullup
not available
GP Slow
VDD_HV_IO
AC18
VREG_CTRL
—
—
Analog Feedthrough
VDD_REG
AC20
RESET_SUP
pulldown
—
Analog Feedthrough
VDD_HV_IO
AC21
VREG_INT_ENABLE
—
—
Analog Feedthrough
VDD_HV_IO
1 Do not connect pin directly to a power supply or ground.
2 PCR234 can be used to control the slew rate of DRAM CLK and DRAM CLKB. See the “System Integration Unit
Lite” chapter of the MPC5675K reference manual.
3 If LBIST is enabled, an external pull between 1K and 100K ohm must be connected from TCK to either power or
ground to avoid LBIST failures.
Table 8. 473 MAPBGA system pins (continued)
Ball
number
Ball name
Weak pull
during reset
Safe mode
default condition
Pad type
Power domain



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