PPC5604BAMLL4R datasheet(34/109 Pages) NXP

34 / 109 page

MPC5604B/C Microcontroller Data Sheet, Rev. 15

Package pinouts and signal descriptions

NXP Semiconductors

2.13

Recommended operating conditions

Table 12. Recommended operating conditions (3.3 V)

Symbol

Parameter

Conditions

Value

Unit

Min

Max

VSS

SR Digital ground on VSS_HV pins

—

VDD

1 100 nF capacitance needs to be provided between each V

DD/VSS pair

SR Voltage on VDD_HV pins with respect to ground

(VSS)

—3.0

3.6

VSS_LV

2 330 nF capacitance needs to be provided between each V

DD_LV/VSS_LV supply pair.

SR Voltage on VSS_LV (low voltage digital supply)

pins with respect to ground (VSS)

—VSS−0.1

VSS+0.1

VDD_BV

3 400 nF capacitance needs to be provided between V

DD_BV and the nearest VSS_LV (higher value may be needed

depending on external regulator characteristics).

SR Voltage on VDD_BV pin (regulator supply) with

respect to ground (VSS)

—3.0

3.6

Relative to VDD VDD−0.1

VDD+0.1

VSS_ADC

SR Voltage on VSS_HV_ADC (ADC reference) pin

with respect to ground (VSS)

—VSS−0.1

VSS+0.1

VDD_ADC

4 100 nF capacitance needs to be provided between V

DD_ADC/VSS_ADC pair.

SR Voltage on VDD_HV_ADC pin (ADC reference)

with respect to ground (VSS)

—3.05

5 Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical

characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL,

device is reset.

3.6

Relative to VDD VDD−0.1

VDD+0.1

VIN

SR Voltage on any GPIO pin with respect to ground

(VSS)

—VSS−0.1

—

Relative to VDD

—VDD+0.1

IINJPAD

SR Injected input current on any pin during overload

condition

—

−55

IINJSUM

SR Absolute sum of all injected input currents during

overload condition

—

−50

TVDD

SR VDD slope to ensure correct power up

6 Guaranteed by device validation.

—3.07

7 Minimum value of TV

DD must be guaranteed until VDD reaches 2.6 V (maximum value of VPORH).

0.25[V/µs]

)

V/s

TA C-Grade Part SR Ambient temperature under bias

fCPU

≤ 64 MHz

−40

°C

TJ C-Grade Part SR Junction temperature under bias

−40

110

TA V-Grade Part SR Ambient temperature under bias

−40

105

TJ V-Grade Part SR Junction temperature under bias

−40

130

TA M-Grade Part SR Ambient temperature under bias

−40

125

TJ M-Grade Part SR Junction temperature under bias

−40

150

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