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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PPC5604BAMLL4R 데이터시트(PDF) 81 Page - NXP Semiconductors |
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PPC5604BAMLL4R 데이터시트(HTML) 81 Page - NXP Semiconductors |
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81 / 109 page  Package pinouts and signal descriptions MPC5604B/C Microcontroller Data Sheet, Rev. 15 NXP Semiconductors 81 3 Maximum value is reached when CSn pad is configured as MEDIUM pad while SCK pad is configured as SLOW. A positive value means that CSn is deasserted before SCK. DSPI0 and DSPI1 have only MEDIUM SCK available. 4 The t CSC delay value is configurable through a register. When configuring tCSC (using PCSSCK and CSSCK fields in DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than ΔtCSC to ensure positive tCSCext. 5 The t ASC delay value is configurable through a register. When configuring tASC (using PASC and ASC fields in DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than ΔtASC to ensure positive tASCext. 6 This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of the DSPI_MCR. 7 SCK and SOUT configured as MEDIUM pad |
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