Data Sheet

ADN8834

Rev. B | Page 27 of 27

OUTLINE DIMENSIONS

A

B

C

D

E

0.660

0.600

0.540

2.58

2.54 SQ

2.50

1

2

3

4

5

BOTTOM VIEW

(BALL SIDE UP)

TOP VIEW

(BALL SIDE DOWN)

END VIEW

0.360

0.320

0.280

BALL A1

IDENTIFIER

SEATING

PLANE

0.390

0.360

0.330

COPLANARITY

0.05

2.00

REF

0.50

BSC

0.270

0.240

0.210

Figure 44. 25-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-25-7)

Dimensions shown in millimeters

0.50

BSC

0.50

0.40

0.30

COMPLIANT

TO JEDEC STANDARDS MO-220-WGGD-8.

BOTTOM VIEW

TOP VIEW

4.10

4.00 SQ

3.90

SEATING

PLANE

0.80

0.75

0.70

0.05 MAX

0.02 NOM

0.20 REF

COPLANARITY

0.08

PIN 1

INDICATOR

1

24

7

12

13

18

19

6

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

0.30

0.25

0.18

PIN 1

INDICATOR

0.20 MIN

2.70

2.60 SQ

2.50

EXPOSED

PAD

Figure 45. 24-Lead Lead-frame Chip Scale Package [LFCSP_WQ]

(CP-24-15)

Dimensions shown in millimeters

ORDERING GUIDE

Model1

Temperature Range2

Package Description

Package

Option

ADN8834ACBZ-R7

−40°C to +125°C

25-Ball Wafer Level Chip Scale Package [WLCSP]

CB-25-7

ADN8834CB-EVALZ

25-Ball WLCSP Evaluation Board: ±1.5 A TEC Current Limit, 3 V TEC Voltage Limit

ADN8834ACPZ-R2

−40°C to +125°C

24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

CP-24-15

ADN8834ACPZ-R7

−40°C to +125°C

24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

CP-24-15

ADN8834CP-EVALZ

24-Lead LFCSP Evaluation Board: ±1.5 A TEC Current Limit, 3 V TEC Voltage Limit

ADN8834MB-EVALZ

Mother Evaluation Board of the ADN8834 for PID tuning

©2015–2018 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.

D12954-0-9/18(B)