286

Figure 4. Timing.

CHARACTERISTICS

(Typical @ 25

°C with V

PARAMETER

MIN.

TYP.

MAX.

UNIT

CONDITIONS

Input Clock Pulse Width (t

ns

Data Setup Time (t

ns

Data Hold Time (t

ns

CLK to SDO Propagation Delay (t

100

ns

DAC Register Load Pulse Width (t

ns

Preset Pulse Width (t

ns

Clock Edge to Load Time (t

ns

Load Edge to Next Clock Edge(t

ns

1

0

1

0

1

0

FS

0

SDI

CLOCK

LOAD

1

0

1

0

1

0

SERIAL

DATA IN

1

0

SERIAL

DATA OUT

CLOCK

LOAD

±1 LSB

ERROR BAND

1

0

PRESET

±1 LSB

ERROR BAND

Table 2. Logic Control Input Truth Table.

SDI

CLK

LOADH

PRESETL

LOGIC OPERATION

X

L

L

H

No Change

Data

L

H

Shift In One Bit from SDI

Shift Out 12–clock delayed data at SDO

X

X

X

L

All DAC Registers Preset to 80

X

L

H

H

Load Serial Register Data into DAC(X) Register

Note 1: "Preset" may not persist at all DACs if LOADH is high when PRESETL returns high.