SP9841 datasheet(29/32 Pages) SIPEX

29 / 32 page

295

input DACs to the proper code. The LM339

does not really drive the LED to full illumina-

tion, due to limited output current, but a pull–up

resistor alone will yield a functional TTL error

signal. External op amps could use the V

REFL

voltage as pseudoground. The outputs of the two

signal DACs must be isolated with resistors if

the two signals are to be multiplexed. This will

reduce the signal gain to 255/256 maximum,

due to the resistive divider created at the com-

parator input. If only a single channel was to be

window–compared, then the maximum gain to

the comparator would be the usual 255/128.

Figure 15 shows the schematic of an evaluation

board, which can be used with an IBM–compat-

ible (XT or AT) computer and the simple

QuickBasic routine of Figure 16 to load each

DAC channel with its desired code. A straight–

through 25-pin cable can be used, or the board

can be plugged directly into the back of the PC.

Data is first latched into each 'HC165 parallel–

to–serial converter. Then a small state machine

is initiated by strobing INI. It clocks the latched

data into the serial data input and strobes the

LOADH input at the DAC. A pair of banana

jacks is used for applying V

DD from an external

supply. A trimpot–adjustable voltage reference

is tied to all eight DAC inputs. On the evaluation

board, jumpers will allow this reference to drive

any V

IN(X) input or the VREFL pin. The other

three op amps in the quad OP–491 are available

for breadboarding circuits, such as in Figures 1

through 14. If the reference voltage is adjusted

down to 0.5V, the DAC and the board should

function with V

DD as low as 2.5V.

Driving Capacitive Loads

Unlike many other products, the SP9841/9842

will not oscillate under purely capacitive load-

ing. However, fullscale step outputs will show

overshoot and ringing of up to 40% at worst–

case purely capacitive loading (between 1,000

and 10,000pF). Figures 17 through 20 show

near fullscale steps under capacitive loads of

between 470pF and 0.47

µF. For capacitance up

to 10,000pF, the addition of a resistive load to

ground at the op amp output will decrease set-

tling times without adversely affecting the posi-

tive–going slew rate. For higher capacitances,

this settling time enhancement comes at the

expense of positive slew rate, as not all instan-

taneous current can be used to charge the capaci-

tor. For all values of capacitive load, settling

time can be dramatically reduced by adding a

small resistor in series with the DAC outputs.

Such series resistors will degrade the current

sinking ability at the DAC outputs for voltages

near ground; while the DACs typically sink

2mA at V

DD =5V at VOUT = 110mV, the addition

of a 50Ohm resistor would require 210mV after

the resistor to sink 2mA. Large capacitances

require lower values of series resistance in order

to obtain critical damping.

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