DP8500 datasheet(32/70 Pages) NSC

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80 RAS and CAS Configuration Modes

The DP8520A21A22A allow the user to configure the

VRAM array to contain one two or four banks of VRAM

Depending on the functions used certain considerations

must be used when determining how to set up the VRAM

array Programming address bits C4 C5 and C6 along with

bank selects B0 – 1 and CAS enables ECAS0 – 1 deter-

mine which RAS or group of RASs and which CAS or group

of CASs will be asserted during an access Different memo-

ry schemes are described The DP8520A21A22A is spec-

ified driving a heavy load of 72 VRAMs representing four

banks of VRAM with 16-bit words and 2 parity bits The

DP8520A21A22A can drive more than 72 VRAMs but the

AC timing must be increased Since the RAS and CAS out-

puts are configurable all RAS and CAS outputs should be

used for the maximum amount of drive

81 BYTE WRITING

By selecting a configuration in which all CAS outputs are

selected during an access each ECAS input enables a pair

of CAS outputs to select a byte in a word size of up to 16

bits In this case the RAS outputs are used to select which

of up to 4 banks is to be used as shown in

Figures 36 and

37 The user can also configure the VRAM array into an 8

bank system as shown in

Figure 38 This setup can be used

along with byte writing for an 8-bit system if the LOW BYTE

and HIGH BYTE are connected to ECAS0 and ECAS1 re-

spectively The user can connect upper address bits to

ECAS01 for use in an 8 bank – 16-bit system but cannot

use byte writing in this case

TLF9338 – 88

FIGURE 36 VRAM Array Setup for 16-Bit System (C6 C5 C4 e 1 1 0 during Programming)

DP8500 데이터시트(PDF) 32 Page - National Semiconductor (TI)