DP8500 datasheet(17/70 Pages) NSC

17 / 70 page

40 Refresh Options (Continued)

422 Staggered RAS Refresh

A staggered refresh staggers each RAS or group of RASs

by a positive edge of CLK as shown in

Figure 11 The num-

ber of RASs which will be asserted on each positive edge

of CLK is determined by the RAS CAS configuration mode

programming bits C4 – C6 If single RAS outputs are select-

ed during programming then each RAS will assert on suc-

cessive positive edges of CLK If two RAS outputs are se-

lected during programming then RAS0 and RAS1 will assert

on the first positive edge of CLK after RFIP is asserted

RAS2 and RAS3 will assert on the second positive edge of

CLK after RFIP is asserted If all RAS outputs were selected

during programming all RAS outputs would assert on the

first positive edge of CLK after RFIP is asserted Each RAS

or group of RASs will meet the programmed RAS low time

and then negate

423 Error Scrubbing during Refresh

The DP8520A21A22A support error scrubbing during all

RAS VRAM refreshes Error scrubbing during refresh is se-

lected through bits C4 – C6 with bit R9 negated during pro-

gramming Error scrubbing can not be used with staggered

refresh (see Section 90) Error scrubbing during refresh al-

lows a CAS or group of CASs to assert during the all RAS

refresh as shown in

Figure 12 This allows data to be read

from the VRAM array and passed through an Error Detec-

tion And Correction Chip EDAC It is important to note that

while an error scrubbing during refresh access is being pe-

formed it is the system designer’s responsibility to properly

control the WE input of the VRAM WE should be high dur-

ing the initial access of the VRAM which could be accom-

plished by gating RFIP if programmed with the processor

access circuitry that creates WE If the EDAC determines

that the data contains a single bit error and corrects that

error the refresh cycle can be extended with the input ex-

tend refresh EXTNDRF and a read-modify-write operation

can be performed and the corrected data can be written

back to the VRAM by bringing WE low The DP8522A has a

24-bit internal refresh address counter that contains the 11

row 11 column and 2 bank addresses The DP8520A21A

have a 22-bit internal refresh address counter that contains

the 10 row 10 column and 2 bank addresses These coun-

ters are configured as bank column row with the row ad-

dress as the least significant bits The bank counter bits are

then used with the programming selection to determine

which CAS or group of CASs will assert during a refresh

TLF9338 – 18

FIGURE 12 Error Scrubbing during Refresh

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