ADPD6000 datasheet(26/89 Pages) AD

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Data Sheet

ADPD6000

THEORY OF OPERATION

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auto-increment to the next register if additional words are accessed

as part of the same access sequence. This automatic address

increment occurs for all addresses except the FIFO address, one

less than the FIFO address and the last used address, which is

0x351. Reads from the FIFO address continue to access the next

byte from the FIFO.

SPI Operations

The SPI single register write operation is shown in Figure 38. The

first two bytes contain the 15-bit register address and specify that a

write is requested. The remaining two bytes are the 16 data bits to

write to the register. The register write occurs only when all 16 bits

are shifted in prior to deassertion of the CS signal.

In addition, multiple registers can be written if additional 16-bit

data is shifted in before deassertion of the CS signal. The register

address automatically increments to the next register after each 16

bits of data.

The SPI single register read operation is shown in Figure 39. The

first two bytes contain the 15-bit register address and specify that

a read is requested. Register bits are shifted out starting with the

MSB. In addition, multiple registers can be read if additional 16-bit

data is shifted out prior to deassertion of the CS signal.

It is recommended that reading from the FIFO is performed byte

wise. There is no requirement to read multiples of 16 bits.

Figure 38. SPI Write Operation

Figure 39. SPI Read Operation

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