USB7002TSLASHKDX datasheet(44/56 Pages) MICROCHIP

44 / 56 page

USB7002

DS00002670G-page 44

 2022 Microchip Technology Inc. and its subsidiaries

9.6.3

RESET AND CONFIGURATION STRAP TIMING

Figure 9-4 illustrates the RESET_N pin timing requirements and its relation to the configuration strap pins. Assertion of

RESET_N is not a requirement. However, if used, it must be asserted for the minimum period specified. Refer to

Section 8.10, Resets for additional information on resets. Refer to Section 3.3, Configuration Straps and Programmable

Functions for additional information on configuration straps.

9.6.4

USB TIMING

All device USB signals conform to the voltage, power, and timing characteristics/specifications as set forth in the Uni-

versal Serial Bus Specification

. Please refer to the Universal Serial Bus Revision 3.2 Specification, available at http://

www.usb.org/developers/docs.

9.6.5

SMBUS TIMING

All device SMBus signals conform to the voltage, power, and timing characteristics/specifications as set forth in the Sys-

tem Management Bus Specification.

Please refer to the System Management Bus Specification, Version 1.0, available

at http://smbus.org/specs.

9.6.6

I2C TIMING

All device I2C signals conform to the 100KHz Standard-mode (Sm) and 400KHz Fast Mode (Fm) voltage, power, and

timing characteristics/specifications as set forth in the I2C-Bus Specification. Please refer to the I2C-Bus Specification,

available at http://www.nxp.com/documents/user_manual/UM10204.pdf.

9.6.7

I2S TIMING

All device I2S signals conform to the voltage, power, and timing characteristics/specifications as set forth in the I2S-Bus

Specification. Please refer to the I2S-Bus Specification, available at http://www.nxp.com/acrobat_download/various/

I2SBUS.pdf.

FIGURE 9-4:

RESET_N CONFIGURATION STRAP TIMING

TABLE 9-6:

RESET_N CONFIGURATION STRAP TIMING

Symbol

Description

Min

Typ

Max

Units

trstia

RESET_N input assertion time

s

tcsh

Configuration strap pins hold after RESET_N deassertion

Note:

The clock input must be stable prior to RESET_N deassertion.

Configuration strap latching and output drive timings shown assume that the Power-On reset has finished

first otherwise the timings in Section 9.6.2, Power-On and Configuration Strap Timing apply.

RESET_N

Configuration

Straps

trstia

tcsh

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