ATAR080-D datasheet(33/68 Pages) ATMEL

33 / 68 page

ATAR080

4675D–4BMCU–12/04

Figure 32. 4-/8-bit Compare Counter

Timer 2 Output Modes

The signal at the timer output is generated via Modulator 2. In the toggle mode, the com-

pare match event toggles the output T2O. For high resolution duty cycle modulation,

8 bits or 12 bits can be used to toggle the output. In the duty cycle burst modulator

modes the DCG output is connected to T2O and switched on and off either by the toggle

flipflop output or the serial data line of the SSI. Modulator 2 also has two modes to out-

put the content of the serial interface as Bi-phase or Manchester code.

The modulator output stage can be configured by the output control bits in the T2M2

stopped either by carrying out a shift register stop (SIR = 1) or compare match event of

stage 1 (CM1) of Timer 2. For this task, Timer 2 mode 3 must be used and the prescaler

has to be supplied with the internal shift clock (SCL).

Figure 33. Timer 2 Modulator Output Stage

4-bit counter

4-bit compare

RES

4-bit register

8-bit counter

8-bit compare

8-bit register

OVF2

CM2

RES

T2RM

T2OTM

Timer 2

output mode

and T2OTM-bit

T2IM

T2CTM

TOG2

INT4

CL2/2

DCG

T2D1, 0

DCGO

P41M2, 1

P4CR

CM1

POUT

CL2/1

MUX

T1OUT

SYSCL

SCL

T2CS1, 0

SYSCL

T2I

Toggle

RES/SET

Bi-phase/

Manchester

modulator

T2TOP

T2OS2, 1, 0

T2M2

T2O

OMSK

SSI

CONTROL

TOG2

DCGO

ATAR080-D 데이터시트(PDF) 33 Page - ATMEL Corporation

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