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L6711

Figure 23. Equivalent Control Loop Gain Block Diagram (left) and Bode Diagram (right)

Compensation network can be simply designed placing

18 LAYOUT GUIDELINES

Since the device manages control functions and high-current drivers, layout is one of the most important

things to consider when designing such high current applications.

A good layout solution can generate a benefit in lowering power dissipation on the power paths, reducing

radiation and a proper connection between signal and power ground can optimize the performance of the

control loops.

Integrated power drivers reduce components count and interconnections between control functions and

drivers, reducing the board space.

Here below are listed the main points to focus on when starting a new layout and rules are suggested for

a correct implementation.

18.1 Power Connections.

These are the connections where switching and continuous current flows from the input supply towards

the load. The first priority when placing components has to be reserved to this power section, minimizing

the length of each connection and loop as much as possible. To minimize noise and voltage spikes (EMI

and losses) these interconnections must be a part of a power plane and anyway realized by wide and thick

copper traces: loop must be anyway minimized. The critical components, i.e. the power transistors, must

be located as close as possible one to the other.

Figure 24 shows the details of the power connections involved and the current loops. The input capaci-

tion in order to eliminate the stray inductance generated by the copper traces. Low ESR and ESL

Rout

Cout

ESR

L/3

REF

PWM

d

dB

ω

K

dB

FB

OSC

IN

R

∆V

V

K

⎥

⎦

⎤

⎢

⎣

⎡

⋅

⋅

=

1

5

4

R

F

R

FB

V

OSC

∆

⋅

V

IN

----------------------------------

5

4

---

ω

T

L

3R

DROOP

ESR

+

()

⋅

--------------------------------------------------------

⋅⋅

⋅

=

C

F

Co

L

3

---

⋅

R

F

--------------------

=