25CSM04T-ISLASHMF datasheet(18/55 Pages) MICROCHIP

18 / 55 page

25CSM04

DS20005817D-page 18

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5.0

WRITE ENABLE AND DISABLE

5.1

Write Enable Instruction (WREN)

The Write Enable Latch (WEL) bit of the STATUS

WRITE, WREX, LOCK, PPWE, WMPR, PPAB and FRZR

instructions. Some of these sequences need further

instructions prior to being executed and are noted in

their corresponding section. The WEL bit is set to a

logic ‘1’ by sending a WREN (06h) instruction to the

25CSM04. First, the CS pin is driven low to select the

device and then a 06h instruction is clocked in on the

SI pin. Then the CS pin is driven high. The WEL bit will

be immediately updated in the STATUS register to a

logic ‘1’.

The WEL bit will be reset to a logic ‘0’ in the following

circumstances:

• Upon power-up as the power-on default condition

is the Write Disable state (Section 1.2.2 “Device

Factory Default Condition”)

• The successful completion of any write sequence

(WRITE, WRSR, WREX, LOCK, WMPR, PPAB, FRZR)

• Executing a Write Disable (WRDI) instruction

(Section 5.2

“Write

Disable

Instruction

(WRDI)”)

• Executing a Software Device Reset (SRST)

instruction

FIGURE 5-1:

WRITE ENABLE (WREN) INSTRUCTION

5.2

Write Disable Instruction (WRDI)

To protect the device against inadvertent write

sequences, the Write Disable (04h) instruction disables

all programming modes by setting the WEL bit to a

logic ‘0’. The WRDI instruction is independent of the

WP pin state.

FIGURE 5-2:

WRITE DISABLE (WRDI) INSTRUCTION

SCK

456

High-Impedance

WREN Opcode (06h)

000

MSb

SCK

234

567

High-Impedance

WRDI Opcode (04h)

MSb

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