25CSM04T-ISLASHMF datasheet(8/55 Pages) MICROCHIP

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25CSM04

DS20005817D-page 8

 2019-2022 Microchip Technology Inc. and its subsidiares

1.1

Power-Up Requirements and

Default Conditions

During a power-up sequence, the VCC supplied to the

25CSM04 should monotonically rise from VSS to the

minimum VCC level as specified in Table 1-1 with a

slew rate no faster than 0.1 V/µs.

1.1.1

DEVICE POWER-ON RESET

To prevent spurious events from happening during a

power-up sequence, the 25CSM04 includes a

Power-on Reset (POR) circuit. Upon power-up, the

device will not respond to any instructions until the VCC

level crosses the internal voltage threshold (VPOR) that

brings the device out of Reset and into Standby mode.

Microchip recommends that CS follows the rise of VCC

at power-up through the use of a pull-up resistor. The

system designer must ensure that no instruction is sent

to the device and CS is driven high until the VCC supply

reaches a stable value greater than the minimum VCC

level. Once VCC has surpassed the minimum level, the

SPI host must wait at least TVCSL before asserting the

CS pin. See Table 1-4 for the values associated with

these power-up parameters.

If an event occurs in the system where the VCC level

supplied to the 25CSM04 drops below the maximum

VPOR level specified, it is recommended that a full

power cycle sequence be performed by first driving the

VCC pin to VSS, waiting at least the minimum TPOFF

time and then performing a new power-up sequence in

compliance with the requirements defined in this

section.

1.1.2

SOFTWARE RESET

The 25CSM04 includes a Software Device Reset

(SRST) instruction that gives the user the opportunity to

reset the device to its power-on default behavior

(Section 1.2 “Device Default State”) without the need

to power cycle the device. To execute this Reset, first,

the CS pin must be driven low to select the device and

then a 7Ch opcode is clocked in on the SI pin.

Then the CS pin can be driven high and the Reset

mechanism will engage. The Reset will have internally

completed by the time the minimum TCSD time is

satisfied.

FIGURE 1-6:

SOFTWARE DEVICE RESET (SRST) INSTRUCTION

TABLE 1-4:

POWER-UP CONDITIONS

Symbol

Parameter

Minimum

Maximum

Units

TVCSL

Minimum VCC to Chip Select Low Time

100

—

µs

VPOR

Power-on Reset Threshold Voltage

—

1.5

TPOFF

Minimum time at VCC = 0V between power cycles

—

Note:

The SRST instruction cannot interrupt the

device while it is in a Busy state

(Section 6.1.4

“Ready/Busy

Status

Latch”).

SCK

567

High-Impedance

SRST Opcode (7Ch)

MSb

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