| 전자부품 데이터시트 검색엔진 |
|
FXLS8967AF 데이터시트(PDF) 47 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
FXLS8967AF 데이터시트(HTML) 47 Page - NXP Semiconductors |
|
47 / 98 page ![]() NXP Semiconductors FXLS8967AF 3-Axis Low-g Accelerometer Bit 7 6 5 4 3 2 1 0 Name WAKE_ODR[3:0] / WAKE_DEC[3:0] SLEEP_ODR[3:0] / SLEEP_DEC[3:0] Reset (BT_MODE = GND) 0 0 0 0 0 0 0 0 Reset (BT_MODE = VDD) 1 1 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Table 51. SENS_CONFIG3 register (address 17h) bit allocation In HPM and LPM modes, a decimation factor is implicit, as specified in Table 52 and Table 53, respectively. In FPM, the decimation factor for WAKE and SLEEP modes is specified via the same bit- fields (see Table 54 for the available settings), and along with the WAKE and SLEEP idle time parameter determines the effective ODR. For example, if SENS_CONFIG2[WAKE_PM] = 10b, selecting FPM in the WAKE operating mode, the SENS_CONFIG3 upper nibble is interpreted as the decimation factor for WAKE mode (WAKE_DEC[3:0]) per Table 54. If a value of 0110b is chosen, for example, a decimation factor of 64 is selected. If WAKE_IDLE[11:0] is set to 256 (decimal), the effective ODR would be 1 / ((256+1) * (312.5 µs) * 64) = 0.195 Hz. The effective ODR is determined in a similar manner for the SLEEP operating mode using the SLEEP_DEC[3:0] and the SLEEP_IDLE[11:0] values. When operating in HPM or LPM with ODR = 3200 Hz, or in FPM with IDLE_TIME = 0, the first data sample is produced after a time delay greater than 1 ODR period using Equation 1. (1) Note: The IDLE_TIME refers to either WAKE_IDLE[11:0] or SLEEP_IDLE[11:0], depending on current operating mode. After this initial delay, all subsequent data samples are made available at the ODR rate. For all other operating modes and settings the first sample is produced within 1 ODR period. Notes: • When the device transitions from WAKE to SLEEP or from SLEEP to WAKE modes there is a 500 µs (nominal) delay between the last acquisition at the WAKE/SLEEP mode ODR and the first acquisition at the SLEEP/WAKE mode ODR. • The ODR may only be changed in Standby mode, with SENS_CONFIG1[ACTIVE] = 0 and SENS_CONFIG4[INT2_FUNC] = 0. ODR[3] ODR[2] ODR[1] ODR[0] ODR Selection (Hz) Decimation selection (samples) Noise RMS (mg)[1][2] IDD (µA) 0 0 0 0 3200 1 12.39 150 0 0 0 1 1600 1 11.77 75 0 0 1 0 800 1 11.19 38 Table 52. WAKE and SLEEP low-power mode ODR and decimation settings FXLS8967AF All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Preliminary data sheet Rev. 1.3 — 22 October 2021 47 / 98 |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |