XRT82L24 datasheet(33/43 Pages) EXAR

부품명	XRT82L24

상세설명	QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

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제조업체	EXAR [Exar Corporation]

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XRT82L24

QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. 1.2.3

Microprocessor Interface I/0 Timing

Intel Interface Timing

The signals used for the Intel microprocessor inter-

face are: Address Latch Enable (ALE), Read Enable

(RD), Write Enable (WR), Chip Select (CS), Address

and Data bits. The microprocessor interface uses

minimum external glue logic and is compatible with

the timings of the 8051 or 80C188 with an 8-16 MHz

clock frequency, and with the timings of x86 or I960

family or microprocessors. The interface timing

shown in Figure 17 and Figure 18 is described in

Table 14.

FIGURE 17. INTEL INTERFACE TIMING (READ)

ALE_AS

RD_DS

A[8:0]

D[7:0]

RDY_DTCK

Not Valid

Valid

Address of Target Register

WR_R/W

t64

t65

t67

t68

t66

t70

t69

t701

FIGURE 18. INTEL INTERFACE TIMING (WRITE)

ALE_AS

A[8:0]

D[7:0]

WR_R/W

Data to be Written

Address of Target Register

RD_DS

t64

t65

t71

t72

t73

t66

t770

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