XRT82L24 datasheet(8/43 Pages) EXAR

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XRT82L24

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QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. 1.2.3

PTS2

SR/DR

Host Mode:

Processor Type Select Input bit 2:

See description for pin 7.

Hardware Mode

Single rail/Dual Rail Control

Connect this pin “Low” to select transmit and receive data format in dual-rail

mode. In this mode, HDB3 encoder and decoder are not available. Connect this

pin "High" to select single-rail data format.

NOTE: Internally pulled -downwith a 50k

Ω resistor.

HW/HOST

Mode Control Input:

This pin is used to select the operating mode of the device, (Hardware Mode or

Host Mode.)

In Hardware Mode, the parallel Microprocessor interface is disabled and

enables all hardware control pin functions.

In Host Mode, the parallel microprocessor interface pins are used for control

functions.

NOTE: Internally pulled "High" with 50k

Ω.

PCLK

Codes

Processor Clock Input.

Input clock for synchronous microprocessor operation. Maximum clock rate is

16 MHz. This pin is internally pull-up for asynchronous microprocessor interface

when no clock is present.

Coding/Decoding Select.

In Hardware Mode, if single-rail data format is selected (pin 8 =”1”), connect

this pin "High" to select AMI encoding and decoding. Connect this pin Low to

select HDB3.

WR_R/W

Write Input (Read/Write).

With Intel bus timing, a Low pulse on WR selects a write operation when CS pin

is Low. When configured in Motorola bus timing, a "High" pulse on R/W selects

a read operation and a Low pulse on R/W selects a write operation when CS is

Low.

RD_DS

Read Input (Data Strobe).

With Intel bus timing, a Low pulse on RD selects a read operation when CS pin

is Low. When configured in Motorola bus timing, a Low pulse on DS indicates a

read or write operation when CS pin is Low.

ALE_AS

Address Latch Input (Address Strobe).

With Intel bus timing, the address inputs are latched into the internal register on

the falling edge of ALE. When configured in Motorola bus timing, the address

inputs are latched into the internal register on the falling edge of AS.

Chip Select Input.

This signal must be Low in order to access the parallel port.

PIN DESCRIPTIONS

PIN #NAME

TYPE

DESCRIPTION

Pin 9

Operating Mode

“Low”

Host Mode

“High”

Hardware Mode

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