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RZ/T2M 데이터시트(PDF) 60 Page - Renesas Technology Corp

부품명 RZ/T2M
상세설명  RZ Arm-based High-end 32 & 64-bit MPUs
PDF  127 Pages
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

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Table 2.21
Bus timing (2 of 2)
Conditions: VOH = VCC33 × 0.5, VOL = VCC33 × 0.5, C = 15 pF (CKIO), 30 pF (others), Tjmin = -40℃
Parameter
Symbol
CKIO = 1/tCKcyc*1
(Max 66 MHz)
Unit
Reference Figure
Min.
Max.
Write data delay time 2
tWDD2
—
10.5
ns
Figure 2.23 to Figure 2.26,
Figure 2.30 to Figure 2.32
Write data hold time 1
tWDH1
1
—
ns
Figure 2.11 to Figure 2.17
Write data hold time 2
tWDH2
2
—
ns
Figure 2.23 to Figure 2.26,
Figure 2.30 to Figure 2.32
Write data hold time 4
tWDH4
0
—
ns
Figure 2.11 to Figure 2.15
WAIT# setup time*3
High-drive output
tWTS
1/2tCKcyc + 4.5 —
ns
Figure 2.12 to Figure 2.18
Normal output
1/2tCKcyc + 8
—
ns
WAIT# hold time
tWTH
1/2tCKcyc + 3.5 —
ns
Figure 2.12 to Figure 2.18
RAS# delay time 1
tRASD1
2
10.5
ns
Figure 2.19 to Figure 2.35
CAS# delay time 1
tCASD1
2
10.5
ns
Figure 2.19 to Figure 2.35
DQM delay time 1
tDQMD1
2
10.5
ns
Figure 2.19 to Figure 2.32
CKE delay time 1
tCKED1
2
10.5
ns
Figure 2.34
AH# delay time
tAHD
1/2tCKcyc
1/2tCKcyc + 10 ns
Figure 2.15
Multiplex address delay time
tMAD
—
10
ns
Figure 2.15
Multiplex address hold time
tMAH
1
—
ns
Figure 2.15
Address setup time to AH#
tAVVH
1/2tCKcyc − 2
—
ns
Figure 2.15
DACK/TEND delay time
tDACD
See section 2.5.4. DMAC
Timing
ns
Figure 2.11 to Figure 2.32
Note:
Notation of 1/2tCKcyc in the delay time, setup time, and hold time shows 1/2 cycles from the clock rising edge, that is, the reference
of clock falling.
Note 1. Take the number of cycles of waiting that suits the system configuration into consideration with regard to the fmax value for CKIO
(the external bus clock). When CKIO is running at 50 MHz or a higher frequency, select high drive output.
Note 2. These are values when SDRAM (CSnBCR.TYPE[2:0] = 100b) is selected in the CSn space bus control register (CSnBCR) and
high-drive output is selected for CKIO.
Note 3. These are values when high-drive output and normal output are respectively selected for CKIO.
Table 2.22
Bus timing (1 of 2)
Conditions: VOH = VCC33 × 0.5, VOL = VCC33 × 0.5, C = 12 pF (CKIO), 12 pF (others), Tjmin = -20℃
Parameter
Symbol
CKIO = 1/tCKcyc*1
(Max 100 MHz)
Unit
Reference Figure
Min.
Max.
Address delay time 1
SDRAM*2
tAD1
1.3
8
ns
Figure 2.11 to Figure 2.35
Other than the above
0
8
ns
Address delay time 2
tAD2
1/2tCKcyc - 0.5 1/2tCKcyc + 8
ns
Figure 2.18
Address setup time
tAS
0
—
ns
Figure 2.11 to Figure 2.14,
Figure 2.18
Chip enable setup time
tCS
0
—
ns
Figure 2.11 to Figure 2.14,
Figure 2.18
Address hold time
tAH
0
—
ns
Figure 2.11 to Figure 2.14
BS delay time
tBSD
—
8
ns
Figure 2.11 to Figure 2.32
CSn# delay time 1
SDRAM*2
tCSD1
1.3
8
ns
Figure 2.11 to Figure 2.35
Other than the above
0
8
ns
RZ/T2M Datasheet
2. Electrical Characteristics
R01DS0383EJ0100 Rev.1.00
Mar 22, 2022
Page 60 of 127



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