4.2

Frame synchronization (WCLK)

The function of the WCLK is simply to identify the beginning of a frame. In particular the frame start at the rising

edge of WCLK, and the WCLK widths supported are:

•

50% duty cycle

•

One slot width (16 BCLK)

•

One BCLK width

In TDM mode, AIS25BA shall output accelerometer data on the SDOUT pin at the following sampling rates:

•

WCLK = 8 kHz

•

WCLK = 16 kHz

•

WCLK = 24 kHz

As depicted in Figure 4. TDM block diagram, the TDM input sampling rate (ODR_8kHz, ODR_16kHz

and ODR_24kHz), and the associated data inputs (dataX_8kHz, dataX_16kHz, dataX_24kHz, dataY_8kHz,

dataY_16kHz, dataY_24kHz, dataZ_8kHz, dataZ_16kHz and dataZ_24kHz ) can be selected in two different

ways:

1.

Using the I²C register wclk_fq (TDM_CTRL_REG (2Eh), bits 2 and 1). In this case the I²C register

ODR_AUTO_EN (CTRL_REG_2 (2Fh), bit 0) is equal to zero, that means that the ODR_auto functionality

is disabled.

2.

Using the output of the ODR_auto block (ODR_AUTO_EN (CTRL_REG_2 (2Fh), bit 0) equal to one).

This latter simply receives as inputs both the MCLK and the WCLK and it computes the current sampling

frequency as a ratio between the MCLK and WCLK.

The possible outputs of the ODR_auto block are:

•

00: sampling rate equal to 8 kHz (MCLK/WCLK = 1536)

•

01: sampling rate equal to 16 kHz (MCLK/WCLK = 768)

•

10: sampling rate equal to 24 kHz (MCLK/WCLK = 512)

Observing Figure 4, it is possible to see, that if a ratio between MCLK and WCLK differ from 1536, 768 and 512,

the sampling rate equal to 8 kHz is selected.

4.3

Serial clock (BCLK)

The sole purpose of the serial clock BCLK is to shift the data out of the serial SDOUT port. To this purpose, the

TDM interface uses an internal counter that is set to one when the rising edge of the WCLK is detected, and it is

reset to zero when the maximum number of BCLK in a WCLK period is reached.

The maximum number of BCLK contained in a WCLK period (cmax input of the TDM in Figure 4. TDM block

diagram) can be expressed as a function of both the BCLK and WCLK frequencies, and can be computed using

the following equation:

cmax=BCLKWCLK−1

In order to support a serial clock BCLK variable in the range [1024 MHz, 12.288 MHz], and consequently to

compute the correct maximum value of the internal TDM counter, two possible solutions can be selected:

•

The cmax value at the input of the TDM interface can be computed on the fly employing the BCLK_AUTO

block (see Figure 4), which is able to compute the cmax value using the above equation. This functionality

by default is enabled, and can be disabled employing the I²C register ODR_AUTO_EN (CTRL_REG_2 (2Fh)

bit 0).

•

The TDM cmax can be programmed through the I²C registers TDM_cmax (24h-25h).

AIS25BA

Frame synchronization (WCLK)

DS14019 - Rev 1

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